Datasheet LT1357 (Analog Devices) - 11

LT1357
U U W U APPLICATIONS INFORMATION
has no effect under normal operation. When driving a pole formed by the output impedance and the capacitive capacitive load (or a low value resistive load) the network load. The zero created by the RC combination adds phase is incompletely bootstrapped and adds to the compensa- to ensure that even for very large load capacitances, the tion at the high impedance node. The added capacitance total phase lag can never exceed 180 degrees (zero phase slows down the amplifier which improves the phase margin) and the amplifier remains stable. margin by moving the unity-gain frequency away from the
W W I S PLI I F ED SCHE ATIC
V+ R1 +IN 500Ω RC –IN OUT C CC 1357 SS01 V–
U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510) 0.400* (10.160) 0.300 – 0.325 0.045 – 0.065 0.130 ± 0.005 MAX (7.620 – 8.255) (1.143 – 1.651) (3.302 ± 0.127) 8 7 6 5 0.065 0.255 ± 0.015* (1.651) (6.477 ± 0.381) 0.009 – 0.015 TYP 0.125 (0.229 – 0.381) (3.175) 0.020 +0.035 MIN (0.508) 1 2 3 4 0.325 –0.015 MIN 0.100 ± 0.010 0.018 ± 0.003 +0.889 N8 1197 8.255 ( ) –0.381 (2.540 ± 0.254) (0.457 ± 0.076) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11