Datasheet LTC3569 (Analog Devices) - 10

LTC3569
operaTion Introduction
Each of the buck regulators supports 100% duty cycle The LTC3569 contains three constant-frequency, current operation (low dropout mode) when their input voltage mode buck DC/DC regulators. Both the P-channel and drops very close to their output voltage. The switching synchronous rectifier (N-channel) switches are internal regulators also include soft-start to limit inrush current to each buck. The operating frequency is determined by when powering on, and short-circuit current protection. the value of the RT resistor, or is fixed to 2.25MHz by pull-
Main Control Loop
ing the RT pin to SVIN, or is synchronized to an external oscillator tied to the MODE pin. Users may select pulse- During normal operation, the top power switch (P-chan- skipping or Burst Mode operation to trade off output ripple nel MOSFET) is turned on at the beginning of a clock for efficiency. Independent programmable reference levels cycle. The P-channel current ramps up as the inductor allow the LTC3569 to suit a variety of applications. charges. The peak inductor current is controlled by the internally compensated error amplifier output, I The LTC3569 offers different power levels, a single 1.2A TH. The current comparator (PCOMP) turns off the P-channel and buck as well as two 600mA bucks. These three bucks turns on the N-channel synchronous rectifier when the may be configured in different parallel configurations, inductor current reaches the I for versatile high current operation. The power stage of TH level minus the offset of the slope compensation ramp. The energy stored in the buck 2 can be configured as a slave to buck 1, by pulling inductor continues to flow through the bottom switch FB2 to SVIN. The power stage of buck 3, can be configured (N-channel) and into the load until either the inductor to be a slave to buck 2, by pulling the FB3 pin to SVIN. To current approaches zero, or the next clock cycle begins. enable the slave power stage, pull the respective EN pin If the inductor current approaches zero the N comparator high. However if the master is disabled, the slave power stage is Hi-Z. MODE BURST SLOPE CLAMP + – + – VREF P COMP ILIM SOFT ON PVIN START SLAVE CLK ILIM P-CHANNEL SD ITH NOR S Q EA EA SWITCHING V P-LATCH FB LOGIC, SW NAND BLANKING, R S GATE ANTI SHOOT-THRU VIN SLAVE SLAVE N-CHANNEL PON SLEEP FROM MASTER NOFF PGND PGOOD ON VREF NOR NCOMP SLAVE – + 3569 F02
Figure 2. Buck Block Diagram
3569fe 10 For more information www.linear.com/LTC3569 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts