Datasheet LTC3522 (Analog Devices) - 8

LTC3522
BLOCK DIAGRAM
8 11 10 12 PV SW1A SW1B V IN1* OUT1 FILTER PGOOD1 6 + 0.9V + A D 0.85A – – + 0.250A – B C LIMIT LIMIT + IZERO VOUT1 ARD I 0A – PGND1 PGND2 REVERSE I FORW BUCK-BOOST – FB1 GATE PWM + 5 DRIVES 1.00V LOGIC + SOFT-START RAMP SHDN1 7 PWM PVIN2* INTERNAL OSCILLATOR 2 15 VCC UVLO SW2 GATE 14 DRIVES BUCK PWM LOGIC SHDN2 16 PGND1 + ZERO CROSSING 0A – + 1.00V ILIMIT 0.594V BANDGAP REFERENCE 0.4A – AND OT SLOPE + 0.9V SHUTDOWN COMPENSATION 0.548V g FB2 m – + 1 + 0.594V + – PGOOD2 4 SOFT-START 0.548V + RAMP – GND PGND1 PGND2 3 13 9 3522 BD *PVIN1 AND PVIN2 MUST BE CONNECTED TOGETHER IN THE APPLICATION. 3522fa 8