Datasheet LTC3403 (Analog Devices) - 7

LTC3403
U U U PI FU CTIO S GDR (Pin 1):
MOSFET Gate Driver. Drives a small external
MODE (Pin 6):
Mode Select Input. To select forced con- P-channel MOSFET. tinuous mode, tie to VIN. Grounding this pin selects Burst
V
Mode operation. Do not leave this pin floating.
IN (Pin 2):
Main Supply Pin. Must be closely decoupled to GND, Pin 3, with a 10µF or greater ceramic capacitor.
REF (Pin 7):
External Reference Input. Controls the output
GND (Pin 3):
Ground Pin. voltage to 3× the applied voltage at REF. Also turns on the bypass MOSFET when VREF > 1.2V.
SW (Pin 4):
Switch Node Connection to Inductor. This pin connects to the drains of the internal main and synchro-
VOUT (Pin 8):
Output Voltage Feedback Pin. An internal nous power MOSFET switches. resistive divider divides the output voltage down by 3 for comparison to the external reference voltage. The drain of
RUN (Pin 5):
Run Control Input. Forcing this pin above the P-channel bypass MOSFET is connected to this pin. 1.5V enables the part. Forcing this pin below 0.3V shuts down the device. In shutdown, all functions are disabled
Exposed Pad (Pin 9):
Connect to GND, Pin 3. drawing <1µA supply current. Do not leave RUN floating.
U U W FU CTIO AL DIAGRA
MODE 6 SLOPE COMP 0.65V OSC OSC FREQ 2 VIN ÷2 – REF + – EN 7 SLEEP + 5Ω V 0.85V + – + OUT ICOMP FB – EA BURST 8 360k S Q R Q 180k SWITCHING RS LATCH LOGIC P-CHANNEL AND ANTI- BLANKING SHOOT- VIN CIRCUIT THRU 4 SW – BCMP 1.2V + + RUN 9 5 IRCMP– 3 GND 1 GDR 3403 BD 3403f 7