Datasheet LT1374 (Analog Devices) - 8

LT1374
W BLOCK DIAGRA
0.01Ω INPUT + – CURRENT 2.9V BIAS INTERNAL SENSE BIAS* REGULATOR V AMPLIFIER CC VOLTAGE GAIN = 20 SLOPE COMP Σ BOOST 0.9V 500kHz SYNC S OSCILLATOR Q1 CURRENT RS DRIVER POWER COMPARATOR FLIP-FLOP CIRCUITRY SWITCH SHUTDOWN + R COMPARATOR + – – VSW 0.4V FREQUENCY SHDN SHIFT CIRCUIT 3.5µA FOLDBACK CURRENT Q2 + LIMIT CLAMP – FB – LOCKOUT + COMPARATOR ERROR VC AMPLIFIER 2.38V g 2.42V m = 2000µMho GND *BIAS PIN IS AVAILABLE ONLY ON THE S0-8 AND FE16 PACKAGES 1374 BD
Figure 1. Block Diagram U U W U APPLICATIO S I FOR ATIO FEEDBACK PIN FUNCTIONS
Please read the following if divider resistors are increased The feedback (FB) pin on the LT1374 is used to set output above the suggested values. voltage and provide several overload protection features. The first part of this section deals with selecting resistors to set output voltage and the remaining part talks about foldback frequency and current limiting created by the FB
Table 1
pin. Please read both parts before committing to a final
OUTPUT R1 % ERROR AT OUTPUT
design. The fixed 5V LT1374-5 has internal divider resis-
VOLTAGE R2 (NEAREST 1%) DUE TO DISCREET 1%
tors and the FB pin is renamed SENSE, connected directly
(V) (k
Ω
) (k
Ω
) RESISTOR STEPS
to the output. 3 4.99 1.21 + 0.23 3.3 4.99 1.82 + 0.08 The suggested value for the output divider resistor (see Figure 2) from FB to ground (R2) is 5k or less, and a 5 4.99 5.36 + 0.39 formula for R1 is shown below. The output voltage error 6 4.99 7.32 – 0.5 caused by ignoring the input bias current on the FB pin is 8 4.99 11.5 – 0.04 less than 0.25% with R2 = 5k. A table of standard 1% 10 4.99 15.8 + 0.83 values is shown in Table 1 for common output voltages. 12 4.99 19.6 – 0.62 15 4.99 26.1 + 0.52 1374fd 8