Datasheet ADP1829 (Analog Devices) - 7

Data Sheet ADP1829 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 P D S M 1 G K 1 E O 2 1 O R S R D N N PIN 1 C T S V NI L E E INDICATOR 32 31 30 29 28 27 26 25 FB1 1 24 POK1 SYNC 2 23 BST1 FREQ 3 22 DH1 ADP1829 GND 4 21 SW1 UV2 5 TOP VIEW 20 CSL1 (Not to Scale) FB2 6 19 PGND1 COMP2 7 18 DL1 TRK2 8 17 PV 9 10 11 12 13 14 15 16 2 2 2 2 2 2 2 2 S K T H L D L S O S D W S N D P B S C G P
3 -00
NOTES
784
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
06 Figure 3. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 FB1 Feedback Voltage Input for Channel 1. Connect a resistor divider from the buck regulator output to GND and tie the tap to FB1 to set the output voltage. 2 SYNC Frequency Synchronization Input. Accepts external signal between 600 kHz and 1.2 MHz or between 1.2 MHz and 2 MHz depending on whether FREQ is low or high, respectively. Connect SYNC to ground if not used. 3 FREQ Frequency Select Input. Low for 300 kHz or high for 600 kHz. 4 GND Ground. Connect to a ground plane directly beneath the ADP1829. Tie the bottom of the feedback dividers to this GND. 5 UV2 Input to the POK2 Undervoltage and Overvoltage Comparators. For the default thresholds, connect UV2 directly to FB2. For some tracking applications, connect UV2 to an extra tap on the FB2 voltage divider string. 6 FB2 Voltage Feedback Input for Channel 2. Connect a resistor divider from the buck regulator output to GND and tie the tap to FB2 to set the output voltage. 7 COMP2 Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to FB2 to compensate Channel 2. 8 TRK2 Tracking Input for Channel 2. To track a master voltage, drive TRK2 from a voltage divider from the master voltage. If the tracking function is not used, connect TRK2 to VREG. 9 SS2 Soft Start Control Input. Connect a capacitor from SS2 to GND to set the soft start period. 10 POK2 Open-Drain Power OK Output for Channel 2. Sinks current when UV2 is out of regulation. Connect a pull-up resistor from POK2 to VREG. 11 BST2 Boost Capacitor Input for Channel 2. Powers the high-side gate driver DH2. Connect a 0.22 μF to 0.47 μF ceramic capacitor from BST2 to SW2 and a Schottky diode from PV to BST2. 12 DH2 High-Side (Switch) Gate Driver Output for Channel 2. 13 SW2 Switch Node Connection for Channel 2. 14 CSL2 Current Sense Comparator Inverting Input for Channel 2. Connect a resistor between CSL2 and SW2 to set the current-limit offset. 15 PGND2 Ground for Channel 2 Gate Driver. Connect to a ground plane directly beneath the ADP1829. 16 DL2 Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 2. 17 PV Positive Input Voltage for Gate Driver DL1 and Gate Driver DL2. Connect PV to VREG and bypass to ground with a 1 μF capacitor. 18 DL1 Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 1. 19 PGND1 Ground for Channel 1 Gate Driver. Connect to a ground plane directly beneath the ADP1829. 20 CSL1 Current Sense Comparator Inverting Input for Channel 1. Connect a resistor between CSL1 and SW1 to set the current-limit offset. 21 SW1 Switch Node Connection for Channel 1. 22 DH1 High-Side (Switch) Gate Driver Output for Channel 1. Rev. D | Page 7 of 28 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT POWER START-UP LOGIC INTERNAL LINEAR REGULATOR OSCILLATOR AND SYNCHRONIZATION ERROR AMPLIFIER SOFT START POWER OK INDICATOR TRACKING MOSFET DRIVERS CURRENT LIMIT APPLICATIONS INFORMATION SELECTING THE INPUT CAPACITOR Selecting the Output LC Filter SELECTING THE MOSFETS SETTING THE CURRENT LIMIT FEEDBACK VOLTAGE DIVIDER COMPENSATING THE VOLTAGE MODE BUCK REGULATOR Type II Compensator Type III Compensator SOFT START VOLTAGE TRACKING COINCIDENT TRACKING RATIOMETRIC TRACKING Setting the Channel 2 Undervoltage Threshold for Ratiometric Tracking THERMAL CONSIDERATIONS PCB LAYOUT GUIDELINES LFCSP PACKAGE CONSIDERATIONS APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE