link to page 1 link to page 1 link to page 1 link to page 3 link to page 3 link to page 3 link to page 3 link to page 5 link to page 5 link to page 6 link to page 6 link to page 8 link to page 9 link to page 9 link to page 11 link to page 12 link to page 12 link to page 13 link to page 13 link to page 14 link to page 16 link to page 16 link to page 18 link to page 20 link to page 20 link to page 21 link to page 22 link to page 36 link to page 37 link to page 40 link to page 41 link to page 43 link to page 44 link to page 44 link to page 1 link to page 20 link to page 20 link to page 14 link to page 12 ADSP-BF592TABLE OF CONTENTS Features ... 1 Related Signal Chains ... 13 Memory .. 1 Signal Descriptions ... 14 Peripherals ... 1 Specifications .. 16 General Description ... 3 Operating Conditions ... 16 Portable Low Power Architecture ... 3 Electrical Characteristics ... 18 System Integration .. 3 Absolute Maximum Ratings ... 20 Blackfin Processor Core .. 3 ESD Sensitivity ... 20 Memory Architecture .. 5 Package Information .. 21 Event Handling .. 5 Timing Specifications ... 22 DMA Controllers .. 6 Output Drive Currents ... 36 Processor Peripherals ... 6 Test Conditions .. 37 Dynamic Power Management .. 8 Environmental Conditions .. 40 Voltage Regulation .. 9 64-Lead LFCSP Lead Assignment ... 41 Clock Signals ... 9 Outline Dimensions .. 43 Booting Modes ... 11 Automotive Products .. 44 Instruction Set Description ... 12 Ordering Guide ... 44 Development Tools ... 12 Additional Information .. 13 REVISION HISTORY7/13—Rev. A to Rev. B Corrected Processor Block Diagram ... 1 Updated Development Tools .. 12 Updated text in Signal Descriptions .. 14 Corrected VDDINT rating in Table 14, Absolute Maximum Ratings ... 20 Rev. B | Page 2 of 44 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory L1 Utility ROM Custom ROM (Optional) I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Watchdog Timer Timers Serial Ports Serial Peripheral Interface (SPI) Ports UART Port Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF592 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 64-Lead LFCSP Lead Assignment Outline Dimensions Automotive Products Ordering Guide
