link to page 3 link to page 4 ADSP-BF592GENERAL DESCRIPTION The ADSP-BF592 processor is a member of the Blackfin® family SYSTEM INTEGRATION of products, incorporating the Analog Devices/Intel Micro The ADSP-BF592 processor is a highly integrated system-on-a- Signal Architecture (MSA). Blackfin processors combine a dual- chip solution for the next generation of digital communication MAC state-of-the-art signal processing engine, the advantages and consumer multimedia applications. By combining industry of a clean, orthogonal RISC-like microprocessor instruction set, standard interfaces with a high performance signal processing and single-instruction, multiple-data (SIMD) multimedia capa- core, cost-effective applications can be developed quickly, with- bilities into a single instruction-set architecture. out the need for costly external components. The system The ADSP-BF592 processor is completely code compatible with peripherals include a watchdog timer; three 32-bit tim- other Blackfin processors. The ADSP-BF592 processor offers ers/counters with PWM support; two dual-channel, full-duplex performance up to 400 MHz and reduced static power con- synchronous serial ports (SPORTs); two serial peripheral inter- sumption. The processor features are shown in Table 1. face (SPI) compatible ports; one UART® with IrDA support; a parallel peripheral interface (PPI); and a 2-wire interface (TWI) Table 1. Processor Features controller. FeatureADSP-BF592BLACKFIN PROCESSOR CORE Timer/Counters with PWM 3 As shown in Figure 2, the Blackfin processor core contains two SPORTs 2 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, SPIs 2 four video ALUs, and a 40-bit shifter. The computation units UART 1 process 8-, 16-, or 32-bit data from the register file. Parallel Peripheral Interface 1 The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the TWI 1 register file operates as 16 independent 16-bit registers. All GPIOs 32 operands for compute operations come from the multiported L1 Instruction SRAM 32K register file and instruction constant fields. L1 Instruction ROM 64K (bytes) Each MAC can perform a 16-bit by 16-bit multiply in each y L1 Data SRAM 32K cycle, accumulating the results into the 40-bit accumulators. mor L1 Scratchpad SRAM 4K Signed and unsigned formats, rounding, and saturation e M L3 Boot ROM 4K are supported. Maximum Instruction Rate1 400 MHz The ALUs perform a traditional set of arithmetic and logical Maximum System Clock Speed 100 MHz operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing Package Options 64-Lead LFCSP tasks. These include bit operations such as field extract and pop- 1 Maximum instruction rate is not available with every possible SCLK selection. ulation count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video By integrating a rich set of industry-leading system peripherals instructions includes byte alignment and packing operations, and memory, Blackfin processors are the platform of choice for 16-bit and 8-bit adds with clipping, 8-bit average operations, next-generation applications that require RISC-like program- and 8-bit subtract/absolute value/accumulate (SAA) operations. mability, multimedia support, and leading-edge signal The compare/select and vector search instructions are also processing in one integrated package. provided. PORTABLE LOW POWER ARCHITECTURE For certain instructions, two 16-bit ALU operations can be per- formed simultaneously on register pairs (a 16-bit high half and Blackfin processors provide world-class power management 16-bit low half of a compute register). If the second ALU is used, and performance. They are produced with a low power and low quad 16-bit operations are possible. voltage design methodology and feature on-chip dynamic power management, which provides the ability to vary both the The 40-bit shifter can perform shifts and rotates and is used to voltage and frequency of operation to significantly lower overall support normalization, field extract, and field deposit power consumption. This capability can result in a substantial instructions. reduction in power consumption, compared with just varying The program sequencer controls the flow of instruction execu- the frequency of operation. This allows longer battery life for tion, including instruction alignment and decoding. For portable appliances. program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction) and subroutine calls. Hardware is provided to support zero over Rev. B | Page 3 of 44 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory L1 Utility ROM Custom ROM (Optional) I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Watchdog Timer Timers Serial Ports Serial Peripheral Interface (SPI) Ports UART Port Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF592 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 64-Lead LFCSP Lead Assignment Outline Dimensions Automotive Products Ordering Guide
