link to page 3 link to page 1 ADSP-BF534/ADSP-BF536/ADSP-BF537GENERAL DESCRIPTION The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are PORTABLE LOW POWER ARCHITECTURE members of the Blackfin® family of products, incorporating the Blackfin processors provide world-class power management Analog Devices, Inc./Intel Micro Signal Architecture (MSA). and performance. They are produced with a low power and low Blackfin processors combine a dual-MAC, state-of-the-art sig- voltage design methodology and feature on-chip dynamic nal processing engine, the advantages of a clean, orthogonal power management, which is the ability to vary both the voltage RISC-like microprocessor instruction set, and single-instruc- and frequency of operation to significantly lower overall power tion, multiple-data (SIMD) multimedia capabilities into a single consumption. This capability can result in a substantial reduc- instruction-set architecture. tion in power consumption, compared with just varying the The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are frequency of operation. This allows longer battery life for completely code and pin compatible. They differ only with portable appliances. respect to their performance, on-chip memory, and presence of the Ethernet MAC module. Specific performance, memory, and SYSTEM INTEGRATION feature configurations are shown in Table 1. The Blackfin processor is a highly integrated system-on-a-chip solution for the next generation of embedded network-con- Table 1. Processor Comparison nected applications. By combining industry-standard interfaces with a high performance signal processing core, cost-effective applications can be developed quickly, without the need for -BF534-BF536-BF537 costly external components. The system peripherals include an IEEE-compliant 802.3 10/100 Ethernet MAC (ADSP-BF536 and FeaturesADSPADSPADSP ADSP-BF537 only), a CAN 2.0B controller, a TWI controller, two UART ports, an SPI port, two serial ports (SPORTs), nine Ethernet MAC — 1 1 general-purpose 32-bit timers (eight with PWM capability), a CAN 1 1 1 real-time clock, a watchdog timer, and a parallel peripheral TWI 1 1 1 interface (PPI). SPORTs 2 2 2 BLACKFIN PROCESSOR PERIPHERALS UARTs 2 2 2 SPI 1 1 1 The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors con- tain a rich set of peripherals connected to the core via several GP Timers 8 8 8 high bandwidth buses, providing flexibility in system configura- Watchdog Timers 1 1 1 tion as well as excellent overall system performance (see RTC 1 1 1 Figure 1). The processors contain dedicated network communi- Parallel Peripheral Interface 1 1 1 cation modules and high speed serial and parallel ports, an GPIOs 48 48 48 interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and power manage- L1 Instruction 16K bytes 16K bytes 16K bytes ment control functions to tailor the performance and power SRAM/Cache characteristics of the processor and system to many application L1 Instruction 48K bytes 48K bytes 48K bytes scenarios. SRAM Memory All of the peripherals, except for the general-purpose I/O, CAN, L1 Data 32K bytes 32K bytes 32K bytes Configuration TWI, real-time clock, and timers, are supported by a flexible SRAM/Cache DMA structure. There are also separate memory DMA channels L1 Data SRAM 32K bytes — 32K bytes dedicated to data transfers between the processor’s various L1 Scratchpad 4K bytes 4K bytes 4K bytes memory spaces, including external SDRAM and asynchronous L3 Boot ROM 2K bytes 2K bytes 2K bytes memory. Multiple on-chip buses running at up to 133 MHz Maximum Speed Grade 500 MHz 400 MHz 600 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external Package Options: peripherals. CSP_BGA 208-Ball 208-Ball 208-Ball CSP_BGA 182-Ball 182-Ball 182-Ball The Blackfin processors include an on-chip voltage regulator in support of the processors’ dynamic power management capabil- By integrating a rich set of industry-leading system peripherals ity. The voltage regulator provides a range of core voltage levels and memory, the Blackfin processors are the platform of choice when supplied from VDDEXT. The voltage regulator can be for next-generation applications that require RISC-like pro- bypassed at the user’s discretion. grammability, multimedia support, and leading-edge signal processing in one integrated package. Rev. J | Page 3 of 68 | February 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Ports Controller Area Network (CAN) TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing External Port Bus Request and Grant Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Port—Master Timing Serial Peripheral Interface Port—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing 10/100 Ethernet MAC Controller Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 182-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
