Datasheet ADSP-BF534, ADSP-BF536, ADSP-BF537 (Analog Devices) - 6

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ADSP-BF534/ADSP-BF536/ADSP-BF537 ADSP-BF534/ADSP-BF537 MEMORY MAP ADSP-BF536 MEMORY MAP 0xFFFF FFFF 0xFFFF FFFF CORE MMR REGISTERS (2M BYTES) CORE MMR REGISTERS (2M BYTES) 0xFFE0 0000 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTES) SYSTEM MMR REGISTERS (2M BYTES) 0xFFC0 0000 0xFFC0 0000 RESERVED RESERVED 0xFFB0 1000 0xFFB0 1000 SCRATCHPAD SRAM (4K BYTES) SCRATCHPAD SRAM (4K BYTES) P 0xFFB0 0000 0xFFB0 0000 A M RESERVED RESERVED Y 0xFFA1 4000 P 0xFFA1 4000 A R INSTRUCTION SRAM/CACHE (16K BYTES) INSTRUCTION SRAM/CACHE (16K BYTES) M O 0xFFA1 0000 M 0xFFA1 0000 E RY RESERVED RESERVED M O 0xFFA0 C000 0xFFA0 C000 L M A INSTRUCTION BANK B SRAM (16K BYTES) E INSTRUCTION BANK B SRAM (16K BYTES) N M 0xFFA0 8000 R 0xFFA0 8000 AL INSTRUCTION BANK A SRAM (32K BYTES) INSTRUCTION BANK A SRAM (32K BYTES) TE N IN 0xFFA0 0000 R 0xFFA0 0000 RESERVED RESERVED TE 0xFF90 8000 IN 0xFF90 8000 DATA BANK B SRAM/CACHE (16K BYTES) DATA BANK B SRAM/CACHE (16K BYTES) 0xFF90 4000 0xFF90 4000 DATA BANK B SRAM (16K BYTES) RESERVED 0xFF90 0000 0xFF90 0000 RESERVED RESERVED 0xFF80 8000 0xFF80 8000 DATA BANK A SRAM/CACHE (16K BYTES) DATA BANK A SRAM/CACHE (16K BYTES) 0xFF80 4000 0xFF80 4000 DATA BANK A SRAM (16K BYTES) RESERVED 0xFF80 0000 0xFF80 0000 RESERVED RESERVED 0xEF00 0800 0xEF00 0800 P BOOT ROM (2K BYTES) BOOT ROM (2K BYTES) A AP 0xEF00 0000 0xEF00 0000 M YM Y RESERVED RESERVED R R 0x2040 0000 0x2040 0000 O ASYNC MEMORY BANK 3 (1M BYTES) M ASYNC MEMORY BANK 3 (1M BYTES) MO E 0x2030 0000 0x2030 0000 M ME ASYNC MEMORY BANK 2 (1M BYTES) ASYNC MEMORY BANK 2 (1M BYTES) L AL 0x2020 0000 0x2020 0000 NA N ASYNC MEMORY BANK 1 (1M BYTES) R ASYNC MEMORY BANK 1 (1M BYTES) R E 0x2010 0000 0x2010 0000 T TE ASYNC MEMORY BANK 0 (1M BYTES) X ASYNC MEMORY BANK 0 (1M BYTES) EX E 0x2000 0000 0x2000 0000 SDRAM MEMORY (16M BYTES TO 512M BYTES) SDRAM MEMORY (16M BYTES TO 512M BYTES) 0x0000 0000 0x0000 0000
Figure 3. ADSP-BF534/ADSP-BF536/ADSP-BF537 Memory Maps memory space, the processor starts executing from the on-chip • Exceptions – Events that occur synchronously to program boot ROM. For more information, see Booting Modes on flow (in other words, the exception is taken before the Page 16. instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause
Event Handling
exceptions. The event controller on the Blackfin processor handles all asyn- • Interrupts – Events that occur asynchronously to program chronous and synchronous events to the processor. The flow. They are caused by input pins, timers, and other Blackfin processor provides event handling that supports both peripherals, as well as by an explicit software instruction. nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that Each event type has an associated register to hold the return servicing of a higher priority event takes precedence over servic- address and an associated return-from-event instruction. When ing of a lower priority event. The controller provides support for an event is triggered, the state of the processor is saved on the five different types of events: supervisor stack. • Emulation – An emulation event causes the processor to The Blackfin processor event controller consists of two stages: enter emulation mode, allowing command and control of the core event controller (CEC) and the system interrupt con- the processor via the JTAG interface. troller (SIC). The core event controller works with the system interrupt controller to prioritize and control all system events. • Reset – This event resets the processor. Conceptually, interrupts from the peripherals enter into the • Nonmaskable Interrupt (NMI) – The NMI event can be SIC, and are then routed directly into the general-purpose inter- generated by the software watchdog timer or by the NMI rupts of the CEC. input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. Rev. J | Page 6 of 68 | February 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Ports Controller Area Network (CAN) TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing External Port Bus Request and Grant Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Port—Master Timing Serial Peripheral Interface Port—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing 10/100 Ethernet MAC Controller Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 182-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide