Datasheet ADSP-BF531, ADSP-BF532, ADSP-BF533 (Analog Devices) - 30

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ADSP-BF531/ ADSP-BF532 /ADSP-BF533 SDRAM Interface Timing Table 25. SDRAM Interface Timing1 VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V Parameter Min Max Min Max Unit
Timing Requirements tSSDAT DATA Setup Before CLKOUT 2.1 1.5 ns tHSDAT DATA Hold After CLKOUT 0.8 0.8 ns Switching Characteristics tDCAD Command, ADDR, Data Delay After CLKOUT2 6.0 4.0 ns tHCAD Command, ADDR, Data Hold After CLKOUT2 1.0 1.0 ns tDSDAT Data Disable After CLKOUT 6.0 4.0 ns tENSDAT Data Enable After CLKOUT 1.0 1.0 ns tSCLK CLKOUT Period3 10.0 7.5 ns tSCLKH CLKOUT Width High 2.5 2.5 ns tSCLKL CLKOUT Width Low 2.5 2.5 ns 1 SDRAM timing for TJ > 105°C is limited to 100 MHz. 2 Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. 3 Refer to Table 13 on Page 21 for maximum fSCLK at various VDDINT.
tSCLK CLKOUT tSSDAT tHSDAT tSCLKL tSCLKH DATA (IN) tDCAD tDSDAT tENSDAT tHCAD DATA (OUT) tDCAD tHCAD COMMAND, ADDRESS (OUT) NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 15. SDRAM Interface Timing Rev. I | Page 30 of 64 | August 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port General-Purpose I/O Port F Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing General-Purpose I/O Port F Pin Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 160-Ball CSP_BGA Ball Assignment 169-Ball PBGA Ball Assignment 176-Lead LQFP Pinout Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide