Datasheet ADAU1701 (Analog Devices) - 3

Data Sheet ADAU1701 REVISION HISTORY
Changes to Figure 5 and Figure 6 ... 10 Changes to Table 11 .. 12
5/16—Rev. B to Rev. C
Replaced Figure 8 to Figure 11 .. 15 Changes to Audio DACs Section and Figure 19 ... 21 Renamed Theory of Operation Section ... 17 Changes to Initialization Section .. 18
6/11—Rev. A to Rev. B
Change to Setting the Master Clock/PLL Mode Section ... 19 Deleted Table 2; Renumbered Sequentially ... 6 Changes to Table 15 .. 23 Changes to Table 4 .. 6 Replaced Figure 22 through Figure 25 ... 26 Changes to EEPROM Format Section .. 28
2/11—Rev. 0 to Rev. A
Deleted Table 20, Renumbered Sequentially ... 29 Moved Figure 1 .. 4 Inserted Figure 28, Renumbered Sequentially .. 29 Changes to Specifications Section ... 5 Changes to Control Register Details Section .. 35 Changes to Table 8, Test Conditions/Comments Column .. 8 Changes to Ordering Guide ... 53 Reordered Figures in Digital Timing Diagrams Section ... 9 Changes to Figure 2 ... 9
7/07—Revision 0: Initial Version
Rev. C | Page 3 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER TEMPERATURE RANGE PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS 2056 (0x0808)—GPIO PIN SETTING REGISTER 2057 TO 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS 2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS 2074 TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS 2076 (0x081C)—DSP CORE CONTROL REGISTER 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL 2084 (0x0824)—AUXILIARY ADC ENABLE 2086 (0x0826)—OSCILLATOR POWER-DOWN 2087 (0x0827)—DAC SETUP MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE