[AK4377A] No. Pin Name I/O Protection Diode Function Power Domain Control Interface TVDD/ VSS3 TVDD/ VSS3 I2C Serial Data Clock Pin B2 SCL I B3 SDA I/O I2C Serial Data Input/Output Pin TVDD TVDD Audio Interface A3 MCKI I External Master Clock Input Pin A1 XTI I X’tal Oscillator Input Pin A2 XTO O X’tal Oscillator Output Pin A4 BCLK I/O Audio Serial Data Clock Pin B5 LRCK I/O Frame Sync Clock Pin B6 SDATA I Audio Serial Data Input Pin TVDD/ VSS3 AVDD/ VSS1 AVDD/ VSS1 TVDD/ VSS3 TVDD/ VSS3 TVDD/ VSS3 TVDD AVDD AVDD TVDD TVDD TVDD Analog Output F1 HPL O Lch Headphone-Amp Output Pin F2 HPR O Rch Headphone-Amp Output Pin E2 HPGND I Headphone-Amp Ground Loop Noise Cancellation Pin CVDD/ VEE2 CVDD/ VEE2 CVDD/ VEE2 CVDD/ VEE2 -Others TVDD/ TVDD VSS3 TVDD/ C4 TESTI1 I TVDD VSS3 AVDD/ D3 TESTO O Test Output Pin AVDD VSS1 Test Input Pin TVDD/ C3 TESTI2 I TVDD It must be tied “L”. VSS3 Note 5. The SCL pin, SDA pin, MCKI pin, BCLK pin, LRCK pin, SDATA pin, HPGND pin, PDN pin, TESTI1 pin and the TESTI2 pin must not be allowed to float. I/O pins should be connected appropriately. C5 PDN I Power down Pin “L”: Power-down, “H”: Power-up Test Input Pin It must be tied “L”. ■ Handing of Unused Pins Unused I/O pins must be connected appropriately. Classification Pin Name HPL, HPR, XTO Analog XTI TESTO Digital MCKI, TESTI1, TESTI2 Setting Open Open (PMOSC bit is fixed to “0”) Open Connect to VSS3 018001092-E-00 2018/02 -8-
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