Datasheet LTM4662 (Analog Devices) - 4

link to page 28 LTM4662
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel. TA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 20. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Control Section
VFB1 Voltage at VFB1 Pin IOUT = 0A, VOUT = 1.5V l 0.592 0.600 0.608 V VFB2 Voltage at VFB2 Pin IOUT = 0A, VOUT = 1.5V l 0.296 0.3 0.304 V VFB2 is Gained Back Up by 2× Internal to 0.6V IFB1, IFB2 (Note 6) 0 ±50 nA VOVL1, VOVL2 Feedback Overvoltage Lockout VFB1 Rising, VFB2 Rising l 0.630 0.645 0.660 V 0.315 0.323 0.330 V ITRACK/SS1, Track Pin Soft-Start Pull-Up Current TRACK/SS1,TRACK/SS2 = 0V 1.0 µA ITRACK/SS2 UVLO INTVCC Undervoltage Lockout INTVCC Falling VIN (Note 6) 3.3 3.7 V INTVCC Rising VIN 4.2 4.5 V tOFF(MIN) Minimum Top Gate Off-Time (Note 6) 90 ns tON(MIN) Minimum Top Gate On-Time (Note 6) 30 ns RFBHI1, RFBHI2 Resistor Between VOUTS1, VOUTS2 59.9 60.4 60.9 kΩ and VFB1, VFB2 Pins for Each Output VPGOOD1, VPGOOD2 PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V Low IPGOOD PGOOD Leakage Current VPGOOD = 5V –2 2 µA VPGOOD PGOOD Trip Level VFB with Respect to Set Output Voltage VFB Ramping Negative –7.5 % VFB Ramping Positive 7.5 %
Internal Linear Regulator
DRVCC Internal DRVCC Voltage 6V < CPWR < 20V 5.0 5.3 5.6 V DRVCC DRVCC Load Regulation ICC = 0mA to 100mA –1.3 –3.0 % Load Regulation VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive 4.4 4.6 4.8 V VEXTVCC(DROP) EXTVCC Dropout ICC = 20mA, VEXTVCC = 5V 80 120 mV VEXTVCC(HYST) EXTVCC Hysteresis 200 mV
Frequency and Clock Synchronization
Frequency Nominal Nominal Frequency RFREQ = 115kΩ 300 350 400 kHz Frequency Low Lowest Frequency RFREQ = 165kΩ (Note 5) 250 kHz Frequency High Highest Frequency RFREQ = 39.2kΩ 900 1000 1100 kHz RMODE_PLLIN MODE_PLLIN Input Resistance MODE_PLLIN to SGND 600 kΩ Channel 2 Phase VOUT2 Phase Relative to VOUT1 PHASMD = SGND 180 Deg PHASMD = Float 180 Deg PHASMD = INTVCC 240 Deg CLKOUT Phase Phase (Relative to VOUT1) PHASMD = SGND 60 Deg PHASMD = Float 90 Deg PHASMD = INTVCC 120 Deg VPLLIN High Clock Input High Level to MODE_PLLIN 2 V VPLLIN Low Clock Input Low Level to MODE_PLLIN 0.5 V Rev. A 4 For more information www.analog.com Document Outline Operation Applications Information Package Description Package Photo Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Revision History Package Photo Design Resources Related Parts