LTC2357-16 Buffered Quad, 16-Bit, 350ksps/Ch Differential ±10.24V ADC with 30VP-P Common Mode Range FeaTuresDescripTion n Simultaneous Sampling of 4 Buffered Channels The LTC®2357-16 is a 16-bit, low noise 4-channel simulta- n 350ksps per Channel Throughput neous sampling successive approximation register (SAR) n 500pA/12nA Max Input Leakage at 85°C/125°C ADC with buffered differential, wide common mode range n ±1LSB INL (Maximum, ±10.24V Range) picoamp inputs. Operating from a 5V low voltage supply, n Guaranteed 16-Bit, No Missing Codes flexible high voltage supplies, and using the internal refer- n Differential, Wide Common Mode Range Inputs ence and buffer, each channel of this SoftSpanTM ADC can be n Per-Channel SoftSpan Input Ranges: independently configured on a conversion-by-conversion n ±10.24V, 0V to 10.24V, ±5.12V, 0V to 5.12V basis to accept ±10.24V, 0V to 10.24V, ±5.12V, or 0V to n ±12.5V, 0V to 12.5V, ±6.25V, 0V to 6.25V 5.12V signals. Individual channels may also be disabled n 94.2dB Single-Conversion SNR (Typical) to increase throughput on the remaining channels. n −110dB THD (Typical) at fIN = 2kHz The integrated picoamp-input analog buffers, wide input n 128dB CMRR (Typical) at fIN = 200Hz common mode range and 128dB CMRR of the LTC2357-16 n Rail-to-Rail Input Overdrive Tolerance al ow the ADC to directly digitize a variety of signals us- n Integrated Reference and Buffer (4.096V) ing minimal board space and power. This input signal n SPI CMOS (1.8V to 5V) and LVDS Serial I/O flexibility, combined with ±1LSB INL, no missing codes n Internal Conversion Clock, No Cycle Latency at 16 bits, and 94.2dB SNR, makes the LTC2357-16 an n 175mW Power Dissipation (44mW/Ch Typical) ideal choice for many high voltage applications requiring n 48-Lead (7mm x 7mm) LQFP Package wide dynamic range. The LTC2357-16 supports pin-selectable SPI CMOS (1.8V applicaTions to 5V) and LVDS serial interfaces. Between one and four n Programmable Logic Controllers lanes of data output may be employed in CMOS mode, n Industrial Process Control allowing the user to optimize bus width and throughput. n Power Line Monitoring All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673, 9197235. n Test and Measurement Typical applicaTion 15V 5V 1.8V TO 5V 0.1µF 0.1µF 2.2µF 0.1µF Integral Nonlinearity vsOutput Code and Channel CMOS OR LVDS I/O INTERFACE 1.00 ±10.24V RANGE FULLY BUFFERS VCC VDD VDDLBYP OVDD LVDS/CMOS TRUE BIPOLAR DRIVE (IN– = 0V) 0.75 ARBITRARY DIFFERENTIAL IN0+ PD ALL CHANNELS S/H +10V +5V IN0– 0.50 LTC2357-16 0V 0V 0.25 SDO0 –10V –5V S/H • • • • • • 0 16-BIT MUX SDO3 TRUE BIPOLAR UNIPOLAR SAR ADC SCKO –0.25 +10V +10V INL ERROR (LSB) S/H SCKI SDI –0.50 0V 0V CS BUSY –0.75 –10V –10V SAMPLE IN3+ S/H CNV CLOCK IN3– –1.00 DIFFERENTIAL INPUTS IN+/IN– WITH VEE REFBUF REFIN GND –32768 –16384 0 16384 32768 WIDE INPUT COMMON MODE RANGE 235716 TA01a OUTPUT CODE FOUR BUFFERED 47µF 0.1µF 235716 TA01b 0.1µF SIMULTANEOUS SAMPLING CHANNELS –15V 235716f For more information www.linear.com/LTC2357-16 1 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Configuration Tables Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Typical Application Related Parts
