LTC2325-14 Quad, 14-Bit + Sign, 5Msps/Ch Simultaneous Sampling ADC FeaTuresDescripTion n 5Msps/Ch Throughput Rate The LTC®2325-14 is a low noise, high speed quad 14-bit n Four Simultaneously Sampling Channels + sign successive approximation register (SAR) ADC with n Guaranteed 14-Bit, No Missing Codes differential inputs and wide input common mode range. n 8VP-P Differential Inputs with Wide Input Operating from a single 3.3V or 5V supply, the LTC2325-14 Common Mode Range has an 8VP-P differential input range, making it ideal for n 81dB SNR (Typ) at fIN = 2.2MHz applications which require a wide dynamic range with high n –88dB THD (Typ) at fIN = 2.2MHz common mode rejection. The LTC2325-14 achieves ±1LSB n Guaranteed Operation to 125°C INL typical, no missing codes at 14 bits and 81dB SNR. n Single 3.3V or 5V Supply The LTC2325-14 has an onboard low drift (20ppm/°C max) n Low Drift (20ppm/°C Max) 2.048V or 4.096V 2.048V or 4.096V temperature-compensated reference. Internal Reference The LTC2325-14 also has a high speed SPI-compatible n 1.8V to 2.5V I/O Voltages serial interface that supports CMOS or LVDS. The fast n CMOS or LVDS SPI-Compatible Serial I/O 5Msps per channel throughput with one cycle latency n Power Dissipation 45mW/Ch (Typ) makes the LTC2325-14 ideally suited for a wide variety n Small 52-Lead (7mm × 8mm) QFN Package of high speed applications. The LTC2325-14 dissipates only 45mW per channel and offers nap and sleep modes applicaTions to reduce the power consumption to 26μW for further n power savings during inactive periods. High Speed Data Acquisition Systems n Communications L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property n Optical Networking of their respective owners. n Multiphase Motor Control Typical applicaTion 10µF 1µF 32k Point FFT fTRUE DIFFERENTIAL INPUTSSMPL = 5Msps,NO CONFIGURATION REQUIRED 3.3V OR 5V 1.8V TO 2.5V fIN = 2.2MHzIN+, IN– 0 VDD GND GND OV SNR = 81.3dB ARBITRARY DIFFERENTIAL DD THD = –87.2dB VDD VDD A + 14-BIT –20 IN1 S/H +SIGN CMOS/LVDS SINAD = 80.5dB A – IN1 SAR ADC SDR/DDR SFDR = 90.3dB REFBUFEN –40 + 14-BIT 0V 0V AIN2 +SIGN A – S/H SDO1 IN2 SAR ADC SDO2 –60 SDO3 LTC2325-14 SDO4 –80 14-BIT CLKOUT BIPOLAR UNIPOLAR A + IN3 V – S/H +SIGN SCK DD VDD AIN3 SAR ADC AMPLITUDE (dBFS) –100 CNV SAMPLE 14-BIT A + CLOCK IN4 +SIGN –120 A – S/H 0V 0V IN4 SAR ADC REF REFOUT1 REFOUT2 REFOUT3 REFOUT4 –140 FOUR SIMULTANEOUS 0 0.5 1 1.5 2 2.5 SAMPLING CHANNELS 1µF 10µF 10µF 10µF 10µF FREQUENCY (MHz) 232514 TA01a 232514 TA01b 232514f For more information www.linear.com/LTC2325-14 1 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Typical Application Related Parts
