link to page 1 link to page 3 link to page 3 link to page 4 link to page 8 link to page 8 link to page 9 link to page 9 link to page 10 link to page 13 link to page 13 link to page 13 link to page 14 link to page 14 link to page 14 link to page 15 link to page 15 link to page 15 link to page 15 link to page 15 link to page 37 link to page 37 link to page 37 link to page 38 link to page 38 link to page 39 link to page 40 link to page 43 link to page 44 link to page 45 link to page 45 link to page 9 link to page 4 link to page 8 link to page 43 link to page 44 link to page 45 ADSP-21261/ADSP-21262/ADSP-21266TABLE OF CONTENTS Summary ... 1 ESD Caution .. 15 General Description ... 3 Maximum Power Dissipation ... 15 Family Core Architecture .. 3 Absolute Maximum Ratings ... 15 Memory and I/O Interface Features ... 4 Timing Specifications ... 15 Target Board JTAG Emulator Connector .. 8 Output Drive Currents ... 37 Development Tools ... 8 Test Conditions .. 37 Additional Information .. 9 Capacitive Loading .. 37 Related Signal Chains .. 9 Environmental Conditions .. 38 Pin Function Descriptions ... 10 Thermal Characteristics .. 38 Address Data Pins as Flags .. 13 144-Lead LQFP Pin Configurations .. 39 Core Instruction Rate to CLKIN Ratio Modes .. 13 136-Ball BGA Pin Configurations ... 40 Address Data Modes .. 13 Outline Dimensions .. 43 Product Specifications ... 14 Surface-Mount Design .. 44 Operating Conditions .. 14 Automotive Products .. 45 Electrical Characteristics ... 14 Ordering Guide ... 45 Package Information ... 15 REVISION HISTORY12/12—Rev. F to Rev. G Corrected Long Word Memory Space in Table 4 in Memory and I/O Interface Features ...4 Updated Development Tools ...8 Added section, Related Signal Chains ...9 Changed the package designator in Figure 36 from BC-136 to BC-136-1. This change in no way affects form, fit, or function. See Outline Dimensions ... 43 Updated Ordering Guide .. 45 Rev. G | Page 2 of 48 | December 2012 Document Outline Summary Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Memory and I/O Interface Features Dual-Ported On-Chip Memory DMA Controller Digital Application Interface (DAI) Serial Ports Serial Peripheral (Compatible) Interface Parallel Port Timers ROM-Based Security Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Address Data Pins as Flags Boot Modes Core Instruction Rate to CLKIN Ratio Modes Address Data Modes Product Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin-to-Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) SPI Interface Protocol—Master SPI Interface Protocol—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Environmental Conditions Thermal Characteristics 144-Lead LQFP Pin Configurations 136-Ball BGA Pin Configurations Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
