link to page 1 link to page 5 link to page 6 link to page 4 ADSP-21261/ADSP-21262/ADSP-21266 elements, but each processing element operates on different Data Address Generators with Zero-Overhead Hardware data. This architecture is efficient at executing math intensive Circular Buffer Support audio algorithms. The ADSP-2126x’s two data address generators (DAGs) are Entering SIMD mode also has an effect on the way data is trans- used for indirect addressing and implementing circular data ferred between memory and the processing elements. When in buffers in hardware. Circular buffers allow efficient program- SIMD mode, twice the data bandwidth is required to sustain ming of delay lines and other data structures required in digital computational operation in the processing elements. Because of signal processing, and are commonly used in digital filters and this requirement, entering SIMD mode also doubles the band- Fourier transforms. The two DAGs of the ADSP-2126x contain width between memory and the processing elements. When sufficient registers to allow the creation of up to 32 circular buf- using the DAGs to transfer data in SIMD mode, two data values fers (16 primary register sets, 16 secondary). The DAGs are transferred with each access of memory or the register file. automatically handle address pointer wraparound, reduce over- head, increase performance, and simplify implementation. Independent, Parallel Computation Units Circular buffers can start and end at any memory location. Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit Flexible Instruction Set (ALU), multiplier, and shifter. These units perform all opera- The 48-bit instruction word accommodates a variety of parallel tions in a single cycle. The three units within each processing operations for concise programming. For example, the element are arranged in parallel, maximizing computational ADSP-2126x can conditionally execute a multiply, an add, and a throughput. Single multifunction instructions execute parallel subtract in both processing elements while branching and fetch- ALU and multiplier operations. In SIMD mode, the parallel ing up to four 32-bit values from memory—all in a single ALU and multiplier operations occur in both processing instruction. elements. These computation units support IEEE 32-bit single precision floating-point, 40-bit extended precision floating- MEMORY AND I/O INTERFACE FEATURES point, and 32-bit fixed-point data formats. The ADSP-2126x adds the following architectural features to Data Register File the SIMD SHARC family core: A general-purpose data register file is contained in each Dual-Ported On-Chip Memory processing element. The register files transfer data between the The ADSP-21262 and ADSP-21266 contain two megabits of computation units and the data buses, and store intermediate internal SRAM and four megabits of internal mask-program- results. These 10-port, 32-register (16 primary, 16 secondary) mable ROM. The ADSP-21261 contain one megabit of internal register files, combined with the ADSP-2126x enhanced Har- SRAM and three megabits of internal mask-programmable vard architecture, allow unconstrained data flow between ROM. Each block can be configured for different combinations computation units and internal memory. The registers in PEX of code and data storage (see memory maps, Table 4 and are referred to as R0–R15 and in PEY as S0–S15. Table 5). Each memory block is dual-ported for single-cycle, Single-Cycle Fetch of Instruction and Four Operands independent accesses by the core processor and I/O processor. The dual-ported memory, in combination with three separate The ADSP-2126x features an enhanced Harvard architecture in on-chip buses, allows two data transfers from the core and one which the data memory (DM) bus transfers data and the pro- from the I/O processor, in a single cycle. gram memory (PM) bus transfers both instructions and data (see Figure 1 on Page 1). With the ADSP-2126x’s separate pro- The ADSP-2126x is available with a variety of multichannel gram and data memory buses and on-chip instruction cache, surround sound decoders, preprogrammed in ROM memory. the processor can simultaneously fetch four operands (two over Table 3 shows the configuration of decoder algorithms. each data bus) and one instruction (from the cache), all in a single cycle. Table 3. Multichannel Surround Sound Decoder Algorithms in On-Chip ROMInstruction CacheAlgorithmsB ROMC ROMD ROM The ADSP-2126x includes an on-chip instruction cache that PCM Yes Yes Yes enables three-bus operation to fetch an instruction and four data values. The cache is selective—only the instructions whose AC-3 Yes Yes Yes fetches conflict with PM bus data accesses are cached. This DTS 96/24 v2.2 v2.3 v2.3 cache allows full-speed execution of core, looped operations AAC (LC) Yes Yes Coefficients only such as digital filter multiply-accumulates, and FFT butterfly WMAPRO 7.1 96 KHz No No Yes processing. MPEG2 BC 2ch Yes Yes No Noise Yes Yes Yes DPL2x/EX DPL2 Yes Yes Neo:6/ES (v2.5046) Yes Yes Yes Rev. G | Page 4 of 48 | December 2012 Document Outline Summary Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Memory and I/O Interface Features Dual-Ported On-Chip Memory DMA Controller Digital Application Interface (DAI) Serial Ports Serial Peripheral (Compatible) Interface Parallel Port Timers ROM-Based Security Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Address Data Pins as Flags Boot Modes Core Instruction Rate to CLKIN Ratio Modes Address Data Modes Product Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin-to-Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) SPI Interface Protocol—Master SPI Interface Protocol—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Environmental Conditions Thermal Characteristics 144-Lead LQFP Pin Configurations 136-Ball BGA Pin Configurations Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
