link to page 1 ADSP-21261/ADSP-21262/ADSP-21266Table 5. Internal Memory Space (ADSP-21262/ADSP-21266)IOP Registers 0x0000 0000–0003 FFFFExtended Precision Normal orLong Word (64 Bits)Instruction Word (48 Bits)Normal Word (32 Bits)Short Word (16 Bits) Block 0 SRAM Block 0 SRAM Block 0 SRAM Block 0 SRAM 0x0004 0000–0x0004 3FFF 0x0008 0000–0x0008 5555 0x0008 0000–0x0008 7FFF 0x0010 0000–0x0010 FFFF Reserved Reserved Reserved Reserved 0x0004 4000–0x0005 7FFF 0x0008 8000–0x000A FFFF 0x0011 0000–0x0015 FFFF Block 0 ROM Block 0 ROM Block 0 ROM Block 0 ROM 0x0005 8000–0x0005 FFFF 0x000A 0000–0x000A AAAA 0x000B 0000–0x000B FFFF 0x0016 0000–0x0017 FFFF Block 1 SRAM Block 1 SRAM Block 1 SRAM Block 1 SRAM 0x0006 0000–0x0006 3FFF 0x000C 0000–0x000C 5555 0x000C 0000–0x000C 7FFF 0x0018 0000–0x0018 FFFF Reserved Reserved Reserved Reserved 0x0006 4000–0x0007 7FFF 0x000C 8000–0x000E FFFF 0x0019 0000–0x001D FFFF Block 1 ROM Block 1 ROM Block 1 ROM Block 1 ROM 0x0007 8000–0x0007 FFFF 0x000E 0000–0x000E AAAA 0x000F 0000–0x000F FFFF 0x001E 0000–0x001F FFFF Digital Application Interface (DAI) The serial ports operate at up to one-quarter of the DSP core clock rate, providing each with a maximum data rate of The Digital application interface provides the ability to connect 50M bits/sec for a 200 MHz core and 37.5M bits/sec for a various peripherals to any of the SHARC DSP’s DAI pins 150 MHz core. Serial port data can be automatically transferred (DAI_P20–1). to and from on-chip memory via a dedicated DMA. Each of the Connections are made using the signal routing unit (SRU, serial ports can work in conjunction with another serial port to shown in the block diagram on Page 1). provide TDM support. One SPORT provides two transmit sig- The SRU is a matrix routing unit (or group of multiplexers) that nals while the other SPORT provides two receive signals. The enables the peripherals provided by the DAI to be intercon- frame sync and clock are shared. nected under software control. This allows easy use of the DAI Serial ports operate in four modes: associated peripherals for a much wider variety of applications • Standard DSP serial mode by using a larger set of algorithms than is possible with noncon- figurable signal paths. • Multichanne l (TDM) mode The DAI also includes six serial ports, two precision clock gen- • I2S mode erators (PCGs), an input data port (IDP), six flag outputs and • Left-justified sample pair mode six flag inputs, and three timers. The IDP provides an additional input path to the ADSP-2126x core, configurable as either eight Left-justified sample pair mode is a mode where in each frame channels of I2S or serial data, or as seven channels plus a single sync cycle, two samples of data are transmitted/received—one 20-bit wide synchronous parallel data acquisition port. Each sample on the high segment of the frame sync, the other on the data channel has its own DMA channel that is independent low segment of the frame sync. Programs have control over var- from the ADSP-2126x’s serial ports. ious attributes of this mode. For complete information on using the DAI, see the Each of the serial ports supports the left-justified sample-pair ADSP-2126x SHARC DSP Peripherals Manual. and I2S protocols (I2S is an industry-standard interface com- monly used by audio codecs, ADCs, and DACs) with two data Serial Ports pins, allowing four left-justified sample-pair or I2S channels (using two stereo devices) per serial port with a maximum of up The ADSP-2126x features six full duplex synchronous serial to 24 audio channels. The serial ports permit little-endian or ports that provide an inexpensive interface to a wide variety of big-endian transmission formats and word lengths selectable digital and mixed-signal peripheral devices such as the Analog from 3 bits to 32 bits. For the left-justified sample pair and I2S Devices AD183x family of audio codecs, ADCs, and DACs. The modes, data-word lengths are selectable between 8 bits and 32 serial ports are made up of two data lines, a clock, and frame bits. Serial ports offer selectable synchronization and transmit sync. The data lines can be programmed to either transmit or modes as well as optional -law or A-law companding selection receive and each data line has its own dedicated DMA channel. on a per channel basis. Serial port clocks and frame syncs can be Serial ports are enabled via 12 programmable and simultaneous internally or externally generated. receive or transmit pins that support up to 24 transmit or 24 receive channels of audio data when all six SPORTs are enabled, or six full duplex TDM streams of 128 channels per frame. Rev. G | Page 6 of 48 | December 2012 Document Outline Summary Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Memory and I/O Interface Features Dual-Ported On-Chip Memory DMA Controller Digital Application Interface (DAI) Serial Ports Serial Peripheral (Compatible) Interface Parallel Port Timers ROM-Based Security Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Address Data Pins as Flags Boot Modes Core Instruction Rate to CLKIN Ratio Modes Address Data Modes Product Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin-to-Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) SPI Interface Protocol—Master SPI Interface Protocol—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Environmental Conditions Thermal Characteristics 144-Lead LQFP Pin Configurations 136-Ball BGA Pin Configurations Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
