X9418 PIN CONFIGURATIONPRINCIPLES OF OPERATION The X9418 is a highly integrated microcircuit DIP/SOIC incorporating two resistor arrays and their associated registers and counters and the serial interface logic VCC 1 24 V+ NC providing direct communication between the host and RL0/VL0 2 23 R 3 NC the XDCP potentiometers. H0/VH0 22 R 4 W0/VW0 21 NC A2 5 20 A0 Serial Interface WP 6 19 NC X9418 The X9418 supports a bidirectional bus oriented SDA 7 18 A3 protocol. The protocol defines any device that sends A1 8 17 SCL data onto the bus as a transmitter and the receiving R 9 L1/VL1 16 NC device as the receiver. The device controlling the RH1/VH1 10 5 NC transfer is a master and the device being controlled is RW1/VW1 11 14 NC the slave. The master will always initiate data transfers VSS 12 13 V- and provide the clock for both transmit and receive operations. Therefore, the X9418 will be considered a TSSOP slave device in all applications. SDA 1 24 WP Clock and Data Conventions A1 2 23 A2 R 3 V Data states on the SDA line can change only during SCL L1/VL1 22 W0/RW0 R 4 H1/VH1 21 VH0/RH0 LOW periods (tLOW). SDA state changes during SCL R 5 20 VL0/RL0 HIGH are reserved for indicating start and stop W1/VW1 VSS 6 19 VCC conditions. X9418 NC 7 18 NC NC 8 17 NC Start Condition NC 9 16 NC All commands to the X9418 are preceded by the start V- 10 15 V+ A0 condition, which is a HIGH to LOW transition of SDA SCL 11 14 12 13 NC while SCL is HIGH (t A3 HIGH). The X9418 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. PIN NAMESStop ConditionSymbolDescription All communications must be terminated by a stop SCL Serial Clock condition, which is a LOW to HIGH transition of SDA SDA Serial Data while SCL is HIGH. A0 - A3 Device Address Acknowledge VH0/RH0 - VH1/RH1, Potentiometer Pins VL0/RL0 - VL1/RL1 (terminal equivalent) Acknowledge is a software convention used to provide a positive handshake between the master and slave VW0/RW0 - Potentiometer Pins devices on the bus to indicate the successful receipt of VW1/RW1 (wiper equivalent) data. The transmitting device, either the master or the WP Hardware Write Protection slave, will release the SDA bus after transmitting eight V+,V- Analog Supplies bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to VCC System Supply Voltage acknowledge that it successfully received the eight bits VSS System Ground of data. NC No Connection FN8194 Rev 2.00 Page 3 of 20 October 12, 2006
