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Datasheet XDPL8218 (Infineon) - 8

ПроизводительInfineon
ОписаниеHigh power factor constant voltage flyback IC with secondary side regulation for cost-effective LED driver
Страниц / Страница45 / 8 — XDPL8218 Digital Flyback Controller IC. XDP™ Digital Power. Functional …
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Язык документаанглийский

XDPL8218 Digital Flyback Controller IC. XDP™ Digital Power. Functional description. Figure 4. Filtered feedback voltage mapping

XDPL8218 Digital Flyback Controller IC XDP™ Digital Power Functional description Figure 4 Filtered feedback voltage mapping

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LED Driver AC/DC, Flyback, 90V to 305V Input, 180 kHz, 1 Output, SOIC-8
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XDPL8218 Digital Flyback Controller IC XDP™ Digital Power Functional description
nABM ton t t sw,ABM tsw,DCM sw,QR1 ton ABM DCM QRM1 1/fsw,min (20kHz typ.) nABM,max ≈ fsw,min/fburst (20kHz typ.) ton,max(Vin) 1/fsw,max ton,min(Vin) ton,min,ABM nABM,min VFB,filtered VFB,min VFB,on VFB,sw VREF (1.2V typ.) (2.0V typ.) (2.428V typ.) VFB,ABM VFB,max,map (0.8V typ.)
Figure 4 Filtered feedback voltage mapping
Note: With the enhanced
PFC
feature enabled and VFB,filtered being stable, in
QRM1
and
DCM
, the VFB,filtered mapped on-time is not constant, but modulated with a function based on the estimated input voltage Vin, estimated output voltage Vout, estimated output current, phase angle and a gain parameter named CEMI. For more details, see
Power factor correction
. •
QRM1
: This mode maximizes the efficiency by switching on the MOSFET at the 1st valley of the primary auxiliary winding voltage VAUX, as shown in
Figure 5
. When VFB,filtered is VFB,on (1.2 V) or more, and its corresponding minimum switching period (based on the purple curve in
Figure 4
) is lower than the system 1st valley switching period tsw,QR1 (see cyan curve in
Figure 4
as an example), the controller operates in
QRM1
and the power transfer is controlled by regulating the on-time. VGD time ton V t AUX sw,QR1 Zero crossing detection 0 V time Valley switching
Figure 5 Switching waveforms in QRM1

DCM
: This mode switches on the MOSFET after the 1st valley of the primary auxiliary winding voltage VAUX, as shown in
Figure 6
. Datasheet 8 Revision 1.0 2018-06-06 Document Outline Features Product validation Potential applications Description Table of contents 1 Pin configuration 2 Functional block diagram 3 Functional description 3.1 Regulated mode 3.2 Configurable gate voltage rising slope at GD pin 3.3 Startup 3.4 Line synchronization 3.5 Input voltage and output voltage estimation 3.5.1 Output voltage estimation 3.5.2 Input voltage estimation 3.6 Power factor correction 3.7 Protection features 3.7.1 Primary MOSFET overcurrent protection 3.7.2 Output undervoltage protection 3.7.3 Output overvoltage protection 3.7.4 Transformer demagnetization time shortage protection 3.7.5 Minimum input voltage startup check and input undervoltage protection 3.7.6 Maximum input voltage startup check and input overvoltage protection 3.7.7 VCC undervoltage lockout 3.7.8 VCC undervoltage protection 3.7.9 VCC overvoltage protection 3.7.10 IC overtemperature protection 3.7.11 Other protections 3.7.12 Protection reactions 3.8 Debug mode 4 List of Parameters 5 Electrical Characteristics and Parameters 5.1 Package Characteristics 5.2 Absolute Maximum Ratings 5.3 Operating Conditions 5.4 DC Electrical Characteristics 6 Package Dimensions 7 References Revision History Glossary ABM CCM CRC CV DCM ECG EMI GUI IC LED OCP1 PC PF PFC QRM1 SSR THD UART USB UVLO Disclaimer
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