TDC-GPX2 − Pin Assignments The TDC-GPX2 is shipped in QFN64 or QFP64 plastic packages Pin Assignments with the following pin assignment. Pin DiagramFigure 4: Pin Diagram of TDC-GPX2 N P N P N P 3 N P K K EN EP N P N P 1 1 2 2 3 L L 3 3 4 4 P P P P D IDX IDX C C D P P P P O O O O D T T F F N O O O O ISABL ISABL ST ST ST ST TV RS RS RE RE D D TG ST ST ST ST 48 33 TVDD33 49 32 TVDD33 TGND TGND TVDD18 TVDD18 REFOSCI CVDD18 REFOSCO CGND PARITY RGND INTERRUPT CVDD18O SSN TVDD18O TDC-GPX2 SCK DVDD18O MOSI RVDD33 MISO DVDD18 DVDD18 DGND DVDD33 DVDD33 DGND DGND LCLKINP LCLKOUTP LCLKINN 64 17 LCLKOUTN 1 16 N P N P N P N P N P N P N P N P 1 1 1 2 2 2 3 3 3 3 4 4 4 E E O O1 E E O O2 E E O O E E O O4 M M M M M M M M A A SD SD A A SD SD A A SD SD A A SD SD FR FR FR FR FR FR FR FR Page 4ams Datasheet Document Feedback [v1-03] 2017-Dec-18 Document Outline General Description Key Benefits & Features Applications Block Diagram Pin Assignments Pin Diagram Pin Description Absolute Maximum Ratings Recommended Operation Conditions Converter Characteristics Power Supply Characteristic Reference Clock and Stop Input Requirements LVDS Data Interface Characteristics Serial Communication Interface Typical Operating Characteristics Histograms Integral Non-Linearity Register Description Configuration Register Overview Detailed Configuration Register Description Read Register Overview Detailed Description Time Measurements and Results Measurements of TDC-GPX2 Output Results Calculation of Time Differences Resolution RMS-Resolution Versus Effective Resolution High Resolution Combining Two Stop Channels Channel Combination for Low Pulse-to-Pulse Spacing Channel Combination for Pulse Width Measurement Input Pins for Time Measurement REFCLKP/N: Reference Clock Input REFOSCI/O: Quartz Driver as Reference Clock RSTIDXP/N: Reference Index Counter Reset STOP1…STOP4P/N: Stop Channels DISABLE/N: Stop Disable Input Levels, CMOS or LVDS LVDS Output Interface Digital Output Interface Output Setup and Configuration: LVDS Output Buffers Differential LCLKIN Input LVDS Single Data Read Output Interface (SDR) LVDS Double Data Read Output Interface (DDR) LVDS Output Test Pattern SPI Communication Interface General Detailed Pin Description Communication Commands (Opcodes) Detailed Command Description Initialization Reset Write / Incremental Write Read / Incremental Read Using SPI Interface for Read-Out of Stop Results Coding of Results Configuration of LSB by REFCLK_DIVISIONS Examples for Codes of Time Measurements Results Maximum Time Differences Conversion Latency and Conversion Rate Converter Latency LVDS Synchronization Latency Conversion Rate Peak Conversion Rate Read-Out Rate Average Conversion Rate Examples for Read-Out Rate with LVDS FIFOs for Adapting Peak and Average Conversion Rate Application Information Configuration Examples Typical Configuration for LVDS Example C++ Code Schematic External Components PCB Layout Package Drawings & Markings Mechanical Data QFN64 QFN64 Tray Information QFP64 QFP64 Tape & Reel Information Soldering & Storage Information Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information Content Guide
