link to page 9 TDC-GPX2 − Recommended Operation Conditions Recommended operating ratings indicate conditions for which Recommended Operation the device is functional, but do not guarantee specific Conditions performance limits. Test conditions for guaranteed specification are expressly denoted. Figure 7: Recommended Operating ConditionsSymbolPinDescriptionMinTypMaxUnitPower-Supply DVDD33, TVDD33, VDD33 Supply Voltage 2.4 3.3 3.6 V RVDD33 Core Supply Voltage powered by DVDD18, TVDD18, VDD18 integrated regulator, pins 1.7 1.8 1.9 V CVDD18 DVDD18O, TVDD18O, CVDD18O Temperature TA Operating free air temperature (1) -40 125 °C Reference & Stop Inputs VID,LVDS LVDS Differential Input Voltage 200 mV LVDS Common Mode Input 2.2 – V STOP1, STOP2, IC,LVDS V V Voltage ID/2 1.25 V STOP3, STOP4, ID/2 REFCLK, RSTIDX, VIL,CMOS CMOS Input Low Voltage 0.4 V DISABLE, VDD33 VIH,CMOS CMOS Input High Voltage V - 0.4 SPI-Interface VIL Digital Input LOW Voltage 0.8 V SCK, MOSI, SSN 0.7 * VIH Digital Input HIGH Voltage V VDD33 INTERRUPT, MISO, CLOAD Load Capacitance to Ground 20 pF PARITY Page 8ams Datasheet Document Feedback [v1-03] 2017-Dec-18 Document Outline General Description Key Benefits & Features Applications Block Diagram Pin Assignments Pin Diagram Pin Description Absolute Maximum Ratings Recommended Operation Conditions Converter Characteristics Power Supply Characteristic Reference Clock and Stop Input Requirements LVDS Data Interface Characteristics Serial Communication Interface Typical Operating Characteristics Histograms Integral Non-Linearity Register Description Configuration Register Overview Detailed Configuration Register Description Read Register Overview Detailed Description Time Measurements and Results Measurements of TDC-GPX2 Output Results Calculation of Time Differences Resolution RMS-Resolution Versus Effective Resolution High Resolution Combining Two Stop Channels Channel Combination for Low Pulse-to-Pulse Spacing Channel Combination for Pulse Width Measurement Input Pins for Time Measurement REFCLKP/N: Reference Clock Input REFOSCI/O: Quartz Driver as Reference Clock RSTIDXP/N: Reference Index Counter Reset STOP1…STOP4P/N: Stop Channels DISABLE/N: Stop Disable Input Levels, CMOS or LVDS LVDS Output Interface Digital Output Interface Output Setup and Configuration: LVDS Output Buffers Differential LCLKIN Input LVDS Single Data Read Output Interface (SDR) LVDS Double Data Read Output Interface (DDR) LVDS Output Test Pattern SPI Communication Interface General Detailed Pin Description Communication Commands (Opcodes) Detailed Command Description Initialization Reset Write / Incremental Write Read / Incremental Read Using SPI Interface for Read-Out of Stop Results Coding of Results Configuration of LSB by REFCLK_DIVISIONS Examples for Codes of Time Measurements Results Maximum Time Differences Conversion Latency and Conversion Rate Converter Latency LVDS Synchronization Latency Conversion Rate Peak Conversion Rate Read-Out Rate Average Conversion Rate Examples for Read-Out Rate with LVDS FIFOs for Adapting Peak and Average Conversion Rate Application Information Configuration Examples Typical Configuration for LVDS Example C++ Code Schematic External Components PCB Layout Package Drawings & Markings Mechanical Data QFN64 QFN64 Tray Information QFP64 QFP64 Tape & Reel Information Soldering & Storage Information Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information Content Guide
