Datasheet ADuM4136 (Analog Devices) - 8

ADuM4136 Data Sheet TYPICAL PERFORMANACE CHARACTERISTICS CH1 = VI+ (2V/DIV) CH1 = VI+ (2V/DIV) 1 1 CH2 = VGATE (5V/DIV) CH2 = VGATE (5V/DIV) 2 2
4 007
CH1 2V CH2 5V 100ns/DIV A CH1 1.68V
-00
CH1 2V CH2 5V 100ns/DIV A CH1 1.68V
75-
10GS/s 100ps/PT
575 13
10GS/s 100ps/PT
135 Figure 4. Input to Output Waveform, 2 nF Load, Figure 7. Input to Output Waveform, 2 nF Load, 5.1 Ω Series Gate Resistor, VDD1 = +5 V, VDD2 = +15 V, VSS2 = −5 V 4.0 Ω Series Gate Resistor, VDD1 = 5 V, VDD2 = 15 V, VSS2 = 0 V
CH1 = VI+ (2V/DIV) CH1 = VI+ (2V/DIV) 1 1 CH2 = VGATE (5V/DIV) CH2 = VGATE (5V/DIV) 2 2
005 008
CH1 2V CH2 5V 100ns/DIV A CH1 1.68V
75-
CH1 2V CH2 5V 100ns/DIV A CH1 1.68V
75-
10GS/s 100ps/PT 10GS/s 100ps/PT
135 135 Figure 5. Input to Output Waveform, 2 nF Load, Figure 8. Input to Output Waveform, 2 nF Load, 5.1 Ω Series Gate Resistor, VDD1 = 5 V, VDD2 = 15 V, VSS2 = 0 V 2.0 Ω Series Gate Resistor, VDD1 = +5 V, VDD2 = +15 V, VSS2 = −5 V
CH1 = VI+ (2V/DIV) CH1 = VI+ (2V/DIV) 1 1 CH2 = VGATE (5V/DIV) CH2 = VGATE (5V/DIV) 2 2
006 009
CH1 2V CH2 5V 100ns/DIV A CH1 1.68V
75-
CH1 2V CH2 5V 100ns/DIV A CH1 1.68V
75-
10GS/s 100ps/PT
135
10GS/s 100ps/PT
135 Figure 6. Input to Output Waveform, 2 nF Load, Figure 9. Input to Output Waveform, 2 nF Load, 4.0 Ω Series Gate Resistor, VDD1 = +5 V, VDD2 = +15 V, VSS2 = −5 V 2.0 Ω Series Gate Resistor, VDD1 = 5 V, VDD2 = 15 V, VSS2 = 0 V Rev. 0 | Page 8 of 16 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Electrical Characteristics Package Characteristics Regulatory Information Insulation and Safety Related Specifications DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics Recommended Operating Conditions Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performanace Characteristics Applications Information PCB Layout Propagation Delay Related Parameters Protection Features Fault Reporting Desaturation Detection Thermal Shutdown Undervoltage Lockout (UVLO) Faults READY Pin Pin Pin VI+ and VI− Operation Gate Resistance Selection Power Dissipation DC Correctness and Magnetic Field Immunity Insulation Lifetime Surface Tracking Insulation Wear Out Calculation and Use of Parameters Example Typical Application Outline Dimensions Ordering Guide