link to page 5 link to page 4 AD7490-EPEnhanced ProductParameterTest Conditions/CommentsMinTypMaxUnit LOGIC OUTPUTS Output High Voltage, VOH ISOURCE = 200 µA VDRIVE − 0.2 V Output Low Voltage, VOL ISINK = 200 µA 0.4 V Floating State Leakage Current WEAK/TRI bit set to 0 ±10 µA Floating State Output Capacitance2 WEAK/TRI bit set to 0 10 pF Output Coding Coding bit set to 1 Straight (natural) binary Coding bit set to 0 Twos complement CONVERSION RATE Conversion Time 16 SCLK cycles, SCLK = 20 MHz 800 ns Track-and-Hold Acquisition Time Sine wave input 300 ns Full-scale step input 300 ns Throughput Rate 1 MSPS POWER REQUIREMENTS VDD 4.75 5.25 V VDRIVE 2.7 5.25 V IDD Digital inputs = 0 V or VDRIVE Normal Mode (Static) SCLK on or off 600 µA Normal Mode (Operational) fSCLK = 20 MHz 2.5 mA (fS = Maximum Throughput) Auto Standby Mode fSAMPLE = 500 kSPS 1.55 mA Static 100 µA Auto Shutdown Mode fSAMPLE = 250 kSPS 960 µA Static 0.5 µA Full Shutdown Mode SCLK on or off 0.02 0.5 µA Power Dissipation Normal Mode (Operational) fSCLK = 20 MHz 12.5 mW Auto Standby Mode (Static) 460 µW Auto Shutdown Mode (Static) 2.5 µW Full Shutdown Mode 2.5 µW 1 Specifications apply for fSCLK up to 20 MHz. However, for serial interfacing requirements, see the Timing Specifications section. 2 Guaranteed by characterization. Rev. B | Page 4 of 12 Document Outline Features Enhanced Product Features Functional Block Diagram General Description Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide
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