Datasheet AD7766-KGD (Analog Devices) - 5

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Known Good Die AD7766-2-KGD TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V ± 5%, VDRIVE = 1.7 V to 3.6 V, VREF+ = 5 V, common-mode input = VREF+/2, TA = −40°C (TMIN) to +105°C (TMAX), unless otherwise noted. Sample tested during initial release to ensure compliance. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.7 V.
Table 3. Parameter Limit at tMIN, tMAX Unit Description
DRDY OPERATION See Figure 2 t1 510 ns typ MCLK rising edge to DRDY falling edge t 1 2 100 ns min MCLK high pulse width t 1 3 900 ns max MCLK low pulse width t4 71 ns typ MCLK rising edge to DRDY rising edge t5 492 ns typ DRDY pulse width tREAD t − t DRDY 5 ns typ DRDY low period, read data during this period t 32 × t DRDY MCLK ns typ DRDY period READ OPERATION See Figure 3 and Figure 4 t6 0 ns min DRDY falling edge to CS setup time t7 6 ns max CS falling edge to SDO tristate disabled t8 60 ns max Data access time after SCLK falling edge (VDRIVE = 1.7 V) 50 ns max Data access time after SCLK falling edge (VDRIVE = 2.3 V) 25 ns max Data access time after SCLK falling edge (VDRIVE = 2.7 V) 24 ns max Data access time after SCLK falling edge (VDRIVE = 3.0 V) t9 10 ns min SCLK falling edge to data valid hold time (VDRIVE = 3.6 V) t10 10 ns min SCLK high pulse width t11 10 ns min SCLK low pulse width tSCLK 1/t8 sec min Minimum SCLK period (not shown in the timing figures) t12 6 ns max Bus relinquish time after CS rising edge t13 0 ns min CS rising edge to DRDY rising edge READ OPERATION WITH CS LOW See Figure 3 t14 0 ns min DRDY falling edge to data valid setup time t15 0 ns max DRDY rising edge to data valid hold time DAISY-CHAIN OPERATION See Figure 5 t16 1 ns min SDI valid to SCLK falling edge setup time t17 2 ns max SCLK falling edge to SDI valid hold time SYNC/PD OPERATION See Figure 6 t18 1 ns typ SYNC/PD falling edge to MCLK rising edge t19 20 ns typ MCLK rising edge to DRDY rising edge going into SYNC/PD mode t20 1 ns min SYNC/PD rising edge to MCLK rising edge t21 510 ns typ MCLK rising edge to DRDY falling edge coming out of SYNC/PD mode tSETTLING 2357 tMCLK Filter settling time (in MCLK periods) after a reset or power-down 1 t2 and t3 allow a ~90% to 10% duty cycle to be used for the MCLK input, where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum MCLK frequency is 1.024 MHz. Rev. 0 | Page 5 of 11 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM RELATED DEVICES TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE