Datasheet AD7766-KGD (Analog Devices) - 6

AD7766-2-KGD Known Good Die Timing Diagrams t2 1 8 × n 1 8 × n MCLK t3 t4 t1 t5 t5 DRDY tREAD
-002
tDRDY
806 13 Figure 2. DRDY vs. MCLK Timing Diagram, n = 4 (Decimate by 32)
tDRDY DRDY tREAD t t13 6 CS t10 1 23 SCLK t11 t8 t9 t7 t12
03
SDO
0
MSB D22 D21 D20 D1 LSB
6- 80 13 Figure 3. Serial Timing Diagram, Reading Data Using CS
CS = 0 tDRDY DRDY tREAD t14 t10 SCLK 1 23 24 t11 t8 t9 t15
4
SDO DATA DATA MSB D22 D21 D20 D1 LSB
-00
INVALID INVALID
806 13 Figure 4. Serial Timing Diagram, Reading Data Setting CS Logic Low Rev. 0 | Page 6 of 11 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM RELATED DEVICES TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE