Datasheet AD9675 (Analog Devices) - 35

Data Sheet AD9675 MASK HITS1: EYE DIAGRAM MASK HITS1: EYE DIAGRAM 400 400 1 1 300 – 300 – 200 200 100 V) 100 V) m m ( E 0 E ( G 0 G A A T T L L –100 –100 VO VO –200 –200 –300 EYE: ALL BITS –300 EYE: ALL BITS OFFSET: 0.0018 MASK: TEMP_MSK OFFSET: –0.0018 MASK: TEMP_MSK ULS: 8000; 993330, TOTAL: 8000; 993330 –400 ULS: 6000; 493327, TOTAL: 6000; 493327
49
–400 –400 –200 0 200 400
1
–200 –100 0 100 200
150
TIME (ps)
381- 1381-
TIME (ps)
1 1 1 Figure 49. Digital Outputs Data Eye, External 100 Ω Terminations at 2.5 Gbps Figure 52. Digital Outputs Data Eye, External 100 Ω Terminations at 5.0 Gbps
PERIOD1: HISTOGRAM PERIOD1: HISTOGRAM 3500 4 4 – 6000 – 3000 5000 2500 4000 2000 S S T T HI HI 1500 3000 1000 2000 500 1000 0
49
0
2
–22.5 –15.0 –7.5 0 7.5 15.0 22.5 –15 –10 –5 0 5 10 15
250 381- 1381-
TIME (ps) TIME (ps)
1 1 1 Figure 50. Digital Outputs Histogram External 100 Ω Terminations Figure 53. Digital Outputs Histogram, External 100 Ω Terminations at 2.5 Gbps at 5.0 Gbps
TJ AT BER1: BATHTUB TJ AT BER1: BATHTUB 1 1 3 3 – 1–2 – 1–2 1–4 1–4 1–6 1–6 R 1–8 R 1–8 BE BE 1–10 1–10 1–12 1–12 1–14 1–14 0.81 0.75 1–16 1–16
0 49
–0.5 0 0.5
3
–0.5 0 0.5
35
UIs
381- 1381-
UIs
1 1 1 Figure 51. Digital Outputs Bathtub Curve, External 100 Ω Terminations Figure 54. Digital Outputs Bathtub Curve, External 100 Ω Terminations at 2.5 Gbps at 5.0 Gbps Rev. A | Page 35 of 60 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications AC Specifications Digital Specifications Switching Specifications CLK±, TX_TRIG± Synchronization Timing Diagram CW Timing Diagram Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics TGC Mode CW Doppler Mode Theory of Operation TGC Operation Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Converter and Lane Configuration Configure the Tail Bits and Control Bits Set Lane Identification Values Set Number of Frames per Multiframe, K Enable Scramble, SCR Set Lane Synchronization Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing Preemphasis Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin GPOx Pins ADDRx Pins TX_TRIG± Pins Analog Test Tone Generation CW Doppler Operation Quadrature Generation I/Q Demodulator and Phase Shifter Digital RF Decimator Vector Profile RF Decimator DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter Digital Test Waveforms Waveform Generator Channel ID and Ramp Generator Digital Block Power Saving Scheme Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Recommended Start-Up Sequence Memory Map Register Table Memory Map Register Descriptions Transfer (Register 0x0FF) Profile Index and Software TX_TRIG (Register 0x10C) Outline Dimensions Ordering Guide