Datasheet AD9674 (Analog Devices) - 7

Data Sheet AD9674 DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, ful temperature range (0°C to 85°C), unless otherwise noted.
Table 2. Parameter1 Temperature Min Typ Max Unit
INPUTS (CLK+, CLK−, TX_TRIG+, TX_TRIG−) Logic Compliance Full CMOS/LVDS/LVPECL Differential Input Voltage2 Full 0.2 3.6 V p-p Input Voltage Range Full GND − 0.2 AVDD1 + 0.2 V Input Common-Mode Voltage Full 0.9 V Input Resistance (Differential) 25°C 15 kΩ Input Capacitance 25°C 4 pF INPUTS (MLO±, RESET±) Logic Compliance Full LVDS/LVPECL Differential Input Voltage2 Full 0.250 2 × AVDD2 V p-p Input Voltage Range Full GND − 0.2 AVDD2 + 0.2 V Input Common-Mode Voltage Full AVDD2/2 V Input Resistance (Single-Ended) 25°C 20 kΩ Input Capacitance 25°C 1.5 pF LOGIC INPUTS (PDWN, STBY, SCLK, SDIO, ADDRx) Logic 1 Voltage Full 1.2 DRVDD + 0.3 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 30 (26 for SDIO) kΩ Input Capacitance 25°C 2 (5 for SDIO) pF LOGIC INPUT (CSB) Logic 1 Voltage Full 1.2 DRVDD + 0.3 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 2 pF LOGIC OUTPUT (SDIO)3 Logic 1 Voltage (IOH = 800 µA) Full 1.79 V Logic 0 Voltage (IOL = 50 µA) Full 0.05 V DIGITAL OUTPUTS (DOUTx+, DOUTx−), ANSI-644 Logic Compliance Full LVDS Differential Output Voltage (VOD) Full 247 454 mV Output Offset Voltage (VOS) Full 1.125 1.375 V Output Coding (Default) Full Offset binary DIGITAL OUTPUTS (DOUTx+, DOUTx−), LOW POWER, REDUCED SIGNAL OPTION Logic Compliance Full LVDS Differential Output Voltage (VOD) Full 150 250 mV Output Offset Voltage (VOS) Full 1.10 1.30 V Output Coding (Default) Full Offset binary LOGIC OUTPUT (GPO0/GPO1/GPO2/GPO3) Full Logic 0 Voltage (IOL = 50 µA) Full 0.05 V 1 For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation. 2 Specified for LVDS and LVPECL only. 3 Specified for 13 SDIO pins sharing the same connection. Rev. A | Page 7 of 47 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC Timing Diagram CW Doppler Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Digital Outputs and Timing Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation DIGITAL RF DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED START-UP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE