Datasheet AD9648-EP (Analog Devices) - 9

Enhanced Product AD9648-EP N – 1 N + 4 tA N + 5 N N + 3 VIN N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCO+ DCO– tSKEW tPD D0+ (LSB) CH A CH B CH A CH B CH A CH B CH A CH B CH A N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 PARALLEL D0– (LSB) INTERLEAVED MODE D13+ (MSB) CH A CH B CH A CH B CH A CH B CH A CH B CH A D13– (MSB) N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 D1+/0+ (LSB) CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0 CHANNEL N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 MULTIPLEXED D1–/D0– (LSB) MODE D13+/D12+ (MSB) CHANNEL A CH A12 CH A13 CH A12 CH A13 CH A12 CH A13 CH A12 CH A13 CH A12 D13–/D12– (MSB) N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 D1+/D0+ (LSB) CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0 CHANNEL N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 MULTIPLEXED D1–/D0– (LSB) MODE D13+/D12+ (MSB) CHANNEL B CH B12 CH B13 CH B12 CH B13 CH B12 CH B13 CH A12 CH A13 CH A12
004
D13–/D12– (MSB) N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12
13386- Figure 4. LVDS Modes for Data Output Timing
CLK+ t t SSYNC HSYNC
005
SYNC
13386- Figure 5. SYNC Input Timing Requirements Rev. B | Page 9 of 17 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE