Datasheet AD8283 (Analog Devices) - 2

link to page 1 link to page 1 link to page 1 link to page 1 link to page 2 link to page 3 link to page 3 link to page 5 link to page 6 link to page 7 link to page 7 link to page 8 link to page 10 link to page 14 link to page 14 link to page 15 link to page 16 link to page 16 link to page 17 link to page 17 link to page 17 link to page 17 link to page 17 link to page 17 link to page 17 link to page 18 link to page 18 link to page 19 link to page 19 link to page 21 link to page 21 link to page 21 link to page 21 link to page 21 link to page 25 link to page 27 link to page 27 link to page 27
AD8283 Data Sheet TABLE OF CONTENTS
Features ...1 Clock Jitter Considerations .. 17 Applications...1 SDIO Pin ... 17 Functional Block Diagram ...1 SCLK Pin ... 17 General Description ..1 CS Pin .. 17 Revision History ..2 RBIAS Pin.. 17 Specifications ...3 Voltage Reference .. 17 AC Specifications ...3 Power and Ground Recommendations .. 18 Digital Specifications ...5 Exposed Paddle Thermal Heat Slug Recommendations .. 18 Switching Specifications...6 Serial Peripheral Interface (SPI) .. 19 Absolute Maximum Ratings ..7 Hardware Interface .. 19 ESD Caution ..7 Memory Map... 21 Pin Configuration and Function Descriptions...8 Reading the Memory Map Table.. 21 Typical Performance Characteristics ...10 Logic Levels ... 21 Theory of Operation ..14 Reserved Locations .. 21 Radar Receive Path AFE ..14 Default Values.. 21 Channel Overview ...15 Application Diagrams.. 25 ADC...16 Outline Dimensions .. 27 Clock Input Considerations ...16 Ordering Guide ... 27 Clock Duty Cycle Considerations ..17 Automotive Products ... 27
REVISION HISTORY 8/15—Rev. B to Rev. C
Changed AD951x/AD952x to AD9515/AD9520-0 ... Throughout Added Table 1; Renumbered Sequential y ...1
10/14—Rev. A to Rev. B
Changes to Addr. (Hex) 0x15, Table 8..23 Changes to Ordering Guide ...27
11/13—Rev. 0 to Rev. A
Changed Maximum fSAMPLE from 80 MSPS to 72 MSPS ... Throughout Changed Clock Pulse Width High/Low (tEH/tEL) at 72 MSPS from 6.25 ns to 6.94ns; Table 3...6 Changes to Figure 25 ...14 Changes to Register Address 10 Bits[5:0] and Register Address 0x12, Bit 3; Table 8 ...23 Updated Outline Dimensions ..27
4/11—Revision 0: Initial Version
Rev. C | Page 2 of 27 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Radar Receive Path AFE Channel Overview Low Noise Amplifier (LNA) Recommendation Antialiasing Filter (AAF) Mux and Mux Controller ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations SDIO Pin SCLK Pin CS Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Serial Peripheral Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Logic Levels Reserved Locations Default Values Application Diagrams Outline Dimensions Ordering Guide Automotive Products