Datasheet AD6641 (Analog Devices) - 5

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AD6641 AC SPECIFICATIONS
AVDD = 1.9 V, DRVDD = 1.9 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 2. AD6641-500 Parameter
1
, 2 Temp Min Typ Max Unit
SNR fIN = 30 MHz 25°C 66.0 dBFS fIN = 125 MHz 25°C 65.9 dBFS Full 65.0 dBFS fIN = 250 MHz 25°C 65.8 dBFS fIN = 450 MHz 25°C 65.1 dBFS SINAD fIN = 30 MHz 25°C 66.0 dBFS fIN = 125 MHz 25°C 65.7 dBFS Full 63.8 dBFS fIN = 250 MHz 25°C 65.3 dBFS fIN = 450 MHz 25°C 64.6 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30 MHz 25°C 10.7 Bits fIN = 125 MHz 25°C 10.6 Bits fIN = 250 MHz 25°C 10.5 Bits fIN = 450 MHz 25°C 10.4 Bits SFDR fIN = 30 MHz 25°C 88 dBc fIN = 125 MHz 25°C 83 dBc Full 77 dBc fIN = 250 MHz 25°C 80 dBc fIN = 450 MHz 25°C 72 dBc WORST HARMONIC (SECOND OR THIRD) fIN = 30 MHz 25°C −92 dBc fIN = 125 MHz 25°C −77 dBc Full −84 dBc fIN = 250 MHz 25°C −80 dBc fIN = 450 MHz 25°C −72 dBc WORST OTHER HARMONIC (SFDR EXCLUDING SECOND AND THIRD) fIN = 30 MHz 25°C −90 dBc fIN = 125 MHz 25°C −90 dBc Full −77 dBc fIN = 250 MHz 25°C −85 dBc fIN = 450 MHz 25°C −78 dBc TWO-TONE IMD fIN1 = 119.8 MHz, fIN2 = 125.8 MHz (−7 dBFS, Each Tone) 25°C −82 dBc ANALOG INPUT BANDWIDTH 25°C 1 GHz 1 All ac specifications tested by driving CLK+ and CLK− differentially. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. Rev. 0 | Page 5 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS SPI TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS SPI REGISTER MAP THEORY OF OPERATION FIFO OPERATION Single Capture Mode Fill Pin Timing Dump Pin Timing SPORT Master Mode (Single Capture) Fill Pulse (1) Empty Signal (2) Full Signal (3) Dump Signal (4)—Transition to High SCLK Signal (5) SDFS Signal (6) Dump Signal (7)—Transition to Low Empty Signal (8)—Transition to High Parallel Master Mode (Single Capture) Fill Pulse (1) Empty Signal (2) Full Signal (3) Dump Signal (4)—Transition to High PCLK± Signal (5) PD[11:0] Signal (6) Dump Signal (7)—Transition to Low Empty Signal (8)—Transition to High Continuous Capture Mode FIFO OUTPUT INTERFACES SPORT Interface Serial Data Frame (Serial Bus Master) CMOS Output Interface LVDS Output Interface ANALOG INPUT AND VOLTAGE REFERENCE VREF CONFIGURATION USING THE SPI OUTLINE DIMENSIONS ORDERING GUIDE