Datasheet AD9286 (Analog Devices) - 7

Data Sheet AD9286 M – 1 M + 4 M + 5 M VIN1+, VIN1– M + 3 t N – 1 A N + 4 M + 1 M + 2 N + 5 N N + 3 VIN2+, VIN2– N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCO+, DCO– tSKEW DATA N – 11 M – 10 N – 10 M – 9 N – 9 M – 8 N – 8 M – 7 N – 7
5 00
tPD
9338- 0 Figure 3. Output Timing Diagram, Sample Mode = Simultaneous, AUXCLKEN = 0
M – 1 M + 4 M + 5 M VIN1+, VIN1– M + 3 t N – 1 A N + 4 M + 1 M + 2 N + 5 N N + 3 VIN2+, VIN2– N + 1 N + 2 tCH tCLK CLK+ CLK– AUXCLK+ AUXCLK– tDCO DCO+, DCO– tSKEW DATA M – 11 N – 11 M – 10 N – 10 M – 9 N – 9 M – 8 N – 8 M – 7
6 -00
tPD
338 09 Figure 4. Output Timing Diagram, Sample Mode = Simultaneous, AUXCLKEN = 1, CLK and AUXCLK in Phase Rev. C | Page 7 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS SPI TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations VOLTAGE REFERENCE RBIAS CLOCK INPUT CONSIDERATIONS Clock Input Options Clocking Modes Interleave Performance DIGITAL OUTPUTS Digital Output Enable Function () BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Voltage Reference (Register 0x18) Bits[7:5]—Reserved Bits[4:0]—Voltage Reference APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE