Datasheet AD9284 (Analog Devices) - 4

AD9284 Data Sheet AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, maximum sample rate, VIN = −1.0 dBFS differential input, unless otherwise noted.
Table 2. Parameter Temperature Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 10.3 MHz 25°C 49.3 dBFS fIN = 70 MHz 25°C 49.3 dBFS fIN = 96.6 MHz Full 48.7 49.3 dBFS fIN = 220 MHz 25°C 49.3 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 10.3 MHz 25°C 49.2 dBFS fIN = 70 MHz 25°C 49.2 dBFS fIN = 96.6 MHz Full 48.5 49.2 dBFS fIN = 220 MHz 25°C 49.2 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10.3 MHz 25°C 7.9 Bits fIN = 70 MHz 25°C 7.9 Bits fIN = 96.6 MHz Full 7.8 7.9 Bits fIN = 220 MHz 25°C 7.9 Bits WORST SECOND OR THIRD HARMONIC fIN = 10.3 MHz 25°C −70 dBc fIN = 70 MHz 25°C −70 dBc fIN = 96.6 MHz Full −70 −61 dBc fIN = 220 MHz 25°C −65 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 10.3 MHz 25°C 70 dBc fIN = 70 MHz 25°C 70 dBc fIN = 96.6 MHz Full 61 69 dBc fIN = 220 MHz 25°C 65 dBc WORST OTHER HARMONIC OR SPUR fIN = 10.3 MHz 25°C −71 dBc fIN = 70 MHz 25°C −71 dBc fIN = 96.6 MHz Full −70 −64 dBc fIN = 220 MHz 25°C −67 dBc CROSSTALK Full −80 dBc Rev. A | Page 4 of 24 Document Outline Features Applications General Description Product Highlights Functional Block Diagram Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications SPI Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Differential Input Configurations Voltage Reference RBIAS Clock Input Considerations Clock Input Options Digital Outputs Digital Output Enable Function () Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Voltage Reference (Register 0x18) Bits[7:5]—Reserved Bits[4:0]—Voltage Reference Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide