Datasheet AD9284 (Analog Devices) - 9

Data Sheet AD9284 Pin No. Mnemonic Type Description
16 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 15 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 14 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 13 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 12 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 11 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 10 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 9 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 18 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 17 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control Pins 30 SCLK Input SPI Serial Clock. 31 SDIO/PWDN Input/output SPI Serial Data I/O (SDIO)/Power-Down Input in External Mode (PWDN). 32 CSB Input SPI Chip Select (Active Low). Do Not Connect 3, 4, 6 DNC N/A Do Not Connect. Do not connect to this pin. Rev. A | Page 9 of 24 Document Outline Features Applications General Description Product Highlights Functional Block Diagram Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications SPI Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Differential Input Configurations Voltage Reference RBIAS Clock Input Considerations Clock Input Options Digital Outputs Digital Output Enable Function () Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Voltage Reference (Register 0x18) Bits[7:5]—Reserved Bits[4:0]—Voltage Reference Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide