Datasheet AD9279 (Analog Devices) - 8

AD9279 ADC TIMING DIAGRAMS N – 1 AIN N tEH tEL CLK– CLK+ tCPD DCO– DCO+ t t FCO FRAME FCO– FCO+ tPD tDATA DOUTx– MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 7 N – 7
002
DOUTx+
3- 0942 Figure 2. 12-Bit Data Serial Stream (Default)
N – 1 AIN N tEH tEL CLK– CLK+ tCPD DCO– DCO+ t t FCO FRAME FCO– FCO+ tPD tDATA DOUTx– LSB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 LSB D0 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 7 N – 7
3
DOUTx+
00 3- 942 0 Figure 3. 12-Bit Data Serial Stream, LSB First Rev. 0 | Page 8 of 44 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS ULTRASOUND THEORY OF OPERATION CHANNEL OVERVIEW TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise Input Overdrive Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Recommendations Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE