Datasheet AD9273 (Analog Devices) - 10

AD9273 ADC TIMING DIAGRAMS N – 1 AIN N tEH tEL CLK– CLK+ tCPD DCO– DCO+ t t FCO FRAME FCO– FCO+ tPD tDATA DOUTx– MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 7 N – 7
02 0
DOUTx+
0- 03 07 Figure 2. 12-Bit Data Serial Stream (Default)
N – 1 AIN N tEH tEL CLK– CLK+ tCPD DCO– DCO+ t t FCO FRAME FCO– FCO+ tPD tDATA DOUTx– D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 (LSB) N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 (MSB)
04
DOUTx+
0 0- 03 07 Figure 3. 12-Bit Data Serial Stream, LSB First Rev. B | Page 10 of 48 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Recommendation Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Crosspoint Switch TGC OPERATION Variable Gain Amplifier Gain Control VGA Noise Antialiasing Filter ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE Caution RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE