Enhanced ProductAD8331-EPParameterTest Conditions/CommentsMinTypMaxUnit1 HILO GAIN RANGE INTERFACE HILO pin Logic Level to Select Gain Range High 2.25 5 V Low 0 1.0 V Input Resistance 50 kΩ OUTPUT CLAMP INTERFACE RCLMP pin, high or low gain Accuracy VOUT = 1 V p-p (clamped) HILO = Low RCLMP = 2.74 kΩ ±50 mV HILO = High RCLMP = 2.21 kΩ ±75 mV MODE INTERFACE MODE pin Logic Level for Gain Slope Positive 0 1.0 V Negative 2.25 5 V Input Resistance 200 kΩ POWER SUPPLY VPSL and VPOS pins Supply Voltage 4.5 5.0 5.5 V Quiescent Current 20 25 mA Power Dissipation No signal 125 mW Power-Down Current VGA and LNA disabled 50 240 400 µA LNA Current (ENBL) 7.5 11 15 mA VGA Current (ENBV) 7.5 14 20 mA Power Supply Rejection Ratio VGAIN = 0 V, f = 100 kHz −68 dB 1 All dBm values are referred to 50 Ω. 2 The absolute gain refers to the theoretical gain expression in Equation 1 of the AD8331 data sheet. 3 Best fit to linear in dB curve. 4 The current is limited to ±1 mA typical. Rev. 0 | Page 5 of 9 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS POWER DERATING CURVES THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE
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