Datasheet AD603 (Analog Devices) - 5

Data Sheet AD603 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS GPOS 1 8 VPOS GPOS 1 8 VPOS AD603 GNEG 2 AD603 7 VOUT GNEG 2 7 VOUT VINP 3 6 TOP VIEW TOP VIEW VNEG VINP 3 6 VNEG
002
(Not to Scale)
003
COMM (Not to Scale) 4 5 FDBK COMM 4 5 FDBK
00539- 00539- Figure 2. 8-Lead SOIC Pin Configuration Figure 3. 8-Lead CERDIP Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 GPOS Gain Control Input High (Positive Voltage Increases Gain). 2 GNEG Gain Control Input Low (Negative Voltage Increases Gain). 3 VINP Amplifier Input. 4 COMM Amplifier Ground. 5 FDBK Connection to Feedback Network. 6 VNEG Negative Supply Input. 7 VOUT Amplifier Output. 8 VPOS Positive Supply Input. Rev. K | Page 5 of 24 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Theory of Operation Noise Performance The Gain Control Interface Programming the Fixed-Gain Amplifier Using Pin Strapping Using the AD603 in Cascade Sequential Mode (Optimal SNR) Parallel Mode (Simplest Gain Control Interface) Low Gain Ripple Mode (Minimum Gain Error) Applications Information A Low Noise AGC Amplifier Caution Evaluation Board Outline Dimensions Ordering Guide