Datasheet AD603 (Analog Devices) - 7

Data Sheet AD603 60 553 PIECE SAMPLE SIZE VOS AT 10dB GAIN VOS VS VGAIN 50 ) % 10dB/DIV ( S E L 40 P AM S F 30 O E AG NT 20 RCE E P 10 0
2 57
2 4 6 8 10 12 14 16 18 20
0 01 9- 9- 53
OFFSET VOLTAGE (mV)
053 0 00 Figure 10. Histogram of VOS at 10 dB Gain and VOS vs. VGAIN Figure 13. Third-Order Intermodulation Distortion at 10.7 MHz (10× Probe Used to HP3585A Spectrum Analyzer, Gain = 0 dB, PIN = 0 dBm)
50 –1.0 553 PIECE SAMPLE SIZE –1.2 ) –1.4 40 ) % (V –1.6 E ES ( L G GPOS –1.8 MP LTA 30 GNEG –2.0 SA VO F T U –2.2 P E O T G –2.4 20 U A T O N –2.6 E IVE C T A –2.8 10 G PER NE –3.0 –3.2 0
3
–3.4
58 01
85 90 95 100 105 110 115
0
0 50 100 200 500 1000 2000
9- 9- 53
PIN GPOS AND PIN GNEG BIAS CURRENT (nA) LOAD RESISTANCE (Ω)
053 00 0 Figure 11. Histogram of GPOS and GNEG Bias Current Figure 14. Typical Output Voltage Swing vs. Load Resistance (Negative Output Swing Limits First)
102 10dB/DIV ) 100 (Ω NCE DA 98 E P M I UT P 96 IN 94
4 1 1 01
100k 1M 10M 100M
0 9- 9- 53 53
FREQUENCY (Hz)
00 00 Figure 12. Third-Order Intermodulation Distortion at 455 kHz Figure 15. Input Impedance vs. Frequency (Gain = −10 dB) (10× Probe Used to HP3585A Spectrum Analyzer, Gain = 0 dB, P IN = 0 dBm) Rev. K | Page 7 of 24 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Theory of Operation Noise Performance The Gain Control Interface Programming the Fixed-Gain Amplifier Using Pin Strapping Using the AD603 in Cascade Sequential Mode (Optimal SNR) Parallel Mode (Simplest Gain Control Interface) Low Gain Ripple Mode (Minimum Gain Error) Applications Information A Low Noise AGC Amplifier Caution Evaluation Board Outline Dimensions Ordering Guide