Datasheet ADA8282 (Analog Devices) - 7

Data Sheet ADA8282 TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.3 V, LNA + PGA gain = 36 dB (LNA gain = 24 dB, PGA gain = 12 dB), TA = 25°C, PGA_BIAS_SEL = b’10, LNA_BIAS_SEL= b’10, unless otherwise noted.
25000 350 T T A = +125°C A = +125°C T T A = +25°C A = –40°C TA = –40°C 300 20000 250 S S T T 15000 HI HI F 200 F R O R O BE BE 150 10000 NUM NUM 100 5000 50 0 0 0 0 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 30 25 20 15 10 05 05 10 15 20 25 30 35
103
0. 0. 0. 0. 0. 0. 0.
107
–0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. GAIN ERROR (dB) PHASE MISMATCH (Degrees)
13132- 13132- Figure 3. Gain Accuracy Distribution Figure 6. Distribution of Channel to Channel Phase Matching
0 3000 TA = +125°C N: 12199 T M: –13.1269 A = +25°C T SD: 19.535 A = –40°C N: 12353 –20 2500 M: –7.49789 SD: 20.0841 S N: 11292 T 2000 –40 M: 0.0246995 HI F SD: 21.4755 B) d R O 1500 –60 BE HD ( T NUM 24dB 1000 –80 18dB 500 –100 30dB 36dB 0 –120 –150 –100 –50 0 50 100 150
10 1
0 1 2 3 4 5
108
VOS (mV)
13132-
FREQUENCY (MHz)
13132- Figure 4. Output Offset Voltage Distribution Figure 7. Total Harmonic Distortion (THD) vs. Frequency for Various Gains, VOUT = −10 dBm
3000 1800 TA = +125°C TA = +25°C T 1600 A = –40°C 2500 1400 ) S 2000 (Ω T 1200 HI F 1000 R O 1500 PEDANCE BE 800 IM NUM 1000 UT 600 INP 400 500 200 0 0 0 1k 10k 100k 1M 10M 100M 1G
109
005 010 015 020 025 030 035 040 045 050
106
0. 0. 0. 0. 0. 0. 0. 0. 0. 0. FREQUENCY (Hz)
13132-
DC GAIN MISMATCH (dB)
13132- Figure 5. Distribution of Channel to Channel Gain Matching Figure 8. Input Impedance vs. Frequency Rev. 0 | Page 7 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS DIGITAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE DEFAULT SPI SETTINGS INPUT IMPEDANCE POWER MODES PROGRAMMABLE GAIN RANGE OUTPUT SWING VARIATION WITH GAIN OFFSET VOLTAGE ADJUSTMENTS VIO Pin SINGLE-ENDED OR DIFFERENTIAL INPUT SHORT-CIRCUIT CURRENTS SPI INTERFACE CHANNEL TO CHANNEL PHASE MATCHING APPLICATIONS INFORMATION INCREASED GAIN USING TWO ADA8282 DEVICES IN SERIES MULTIPLEXING INPUTS USING MULTIPLE ADA8282 DEVICES BASIC CONNECTIONS FOR A TYPICAL APPLICATION REGISTER MAP REGISTER SUMMARY REGISTER DETAILS Register 0x00: Interface Configuration Register Register 0x01: Soft Reset Register Register 0x04: Chip ID Low Register Register 0x05: Chip ID High Register Register 0x06: Revision Register Register 0x10: LNA Offset 0 Register Register 0x11: LNA Offset 1 Register Register 0x12: LNA Offset 2 Register Register 0x13: LNA Offset 3 Register Register 0x14: PGA Bias Register Register 0x15: PGA Gain Register Register 0x17: Enable Channel Register Register 0x18: Enable Bias Generator Register Register 0x1D: GPIO Write Register Register 0x1E: GPIO Read Register OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS