Datasheet ADL5336 (Analog Devices) - 5

Data Sheet ADL5336 TIMING DIAGRAMS t t CLK PW CLK tLH tLS LE t t DS DH DATA WRITE BIT LSB LSB + 1 LSB + 2 LSB + 3 MSB – 3 MSB – 2 MSB – 1 MSB NOTES 1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A WRITE
002
OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE 8-BIT WORD IS THEN REGISTERED INTO THE DATA PIN ON CONSECUTIVE RISING EDGES OF THE CLOCK.
09550- Figure 2. Write Mode Timing Diagram
t t PW CLK tD CLK tLH tLS LE t t DS DH DATA READ BIT DC DC DC DC DC DC DC DC SDO LSB LSB + 1 LSB + 2 LSB + 3 MSB – 3 MSB – 2 MSB – 1 MSB NOTES 1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A READ
003
OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE 8-BIT WORD IS THEN UPDATED AT THE SDO PIN ON CONSECUTIVE FALLING EDGES OF THE CLOCK.
09550- Figure 3. Read Mode Timing Diagram Rev. C | Page 5 of 30 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT DESCRIPTION GAIN CONTROL INTERFACE INPUT AND OUTPUT IMPEDANCES AGC OPERATION REGISTER MAP AND CODES APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DETECTOR OUTPUT AND GAIN PIN COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS MODE AND ENABLE CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) EFFECT OF CAGC ON EVM AGC INSENSITIVITY TO MODULATION TYPE EFFECT OF SETPOINT ON EVM CASCADED VGA/AGC PERFORMANCE EVALUATION BOARD LAYOUT BILL OF MATERIALS (BOM) EVALUATION BOARD CONTROL SOFTWARE OUTLINE DIMENSIONS ORDERING GUIDE