AD8432Data SheetPIN CONFIGURATION AND FUNCTION DESCRIPTIONS11111BSHHHLNPPOMMEVOGGG432102222921INH1 118 GOL1INL1 217 OPL1IND1 3AD843216 COM1TOP VIEWCOMM 415 COM2(Not to Scale)INL2 514 OPL2INH2 613 GOL2789011121222222DSHHHLNPPMIVOMOGGG 2 NOTES 00 1- 1. EXPOSED PAD MUST BE CONNECTED 34 TO GROUND. 08 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No.MnemonicDescription 1 INH1 LNA1 Noninverting Input. 2 INL1 LNA1 Inverting Input (AC-Coupled to Ground). 3, 7 IND1, IND2 Integrated Input Clamping Back-to-Back Diodes. 4 COMM Input Ground. 5 INL2 LNA2 Inverting Input (AC-Coupled to Ground). 6 INH2 LNA2 Noninverting Input. 8 VPS2 5 V Supply. 9 OPH2 Noninverting Output of LNA2. 10 GOH2 Gain Setting Pin for LNA2. 11 GMH2 Gain Setting Pin for LNA2. 12 GML2 Gain Setting Pin for LNA2. 13 GOL2 Gain Setting Pin for LNA2. 14 OPL2 Inverting Output of LNA2. 15 COM2 LNA2 Output Ground. 16 COM1 LNA1 Output Ground. 17 OPL1 Inverting Output of LNA1. 18 GOL1 Gain Setting Pin for LNA1. 19 GML1 Gain Setting Pin for LNA1. 20 GMH1 Gain Setting Pin for LNA1. 21 GOH1 Gain Setting Pin for LNA1. 22 OPH1 Noninverting Output of LNA1. 23 VPS1 5 V Supply. 24 ENB Enable. EPAD Exposed pad must be connected to ground. Rev. D | Page 6 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION LOW NOISE AMPLIFIER (LNA) GAIN SETTING TECHNIQUE ACTIVE INPUT RESISTANCE MATCHING APPLICATIONS INFORMATION TYPICAL SETUP I/Q DEMODULATION FRONT END DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION EVALUATION BOARD CONNECTION AND OPERATION Power Supply Input Termination Setting the Amplifier Gain Output SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE NOTES NOTES NOTES
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