VEML6035 www.vishay.com Vishay Semiconductors I2C TIMING CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) STANDARD MODE (1)FAST MODE (1)PARAMETERSYMBOLUNITMIN.MAX.MIN.MAX. Clock frequency f(SMBCLK) 10 100 10 400 kHz Bus free time between start and stop condition t(BUF) 4.7 - 1.3 - μs Hold time after (repeated) start condition; t after this period, the first clock is generated (HDSTA) 4.0 - 0.6 - μs Repeated start condition setup time t(SUSTA) 4.7 - 0.6 - μs Stop condition setup time t(SUSTO) 4.0 - 0.6 - μs Data hold time t(HDDAT) 0 3450 0 900 ns Data setup time t(SUDAT) 250 - 100 - ns I2C clock (SCK) low period t(LOW) 4.7 - 1.3 - μs I2C clock (SCK) high period t(HIGH) 4.0 - 0.6 - μs Detect clock / data low timeout t(TIMEOUT) 25 35 - - ms Clock / data fall time t(F) - 300 - 300 ns Clock / data rise time t(R) - 1000 - 300 ns Note (1) Data based on standard I2C protocol requirement, not tested in production t t t (LOW) (R) (F) V I2C bus IH clock V (SLCK) IL t t (SUSTA) (HDSTA) t(HIGH) t t (SUSTO) (BUF) t(HDDAT) t(SUDAT) I2C bus VIH data (SDAT) VIL { { { { P S S P Stop condition Start condition Start Stop t(LOSEXT) SCLK SDA ACK ACK t t t (LOWMEXT) (LOWMEXT) (LOWMEXT) I2C bus clock (SLCK) I2C bus data (SDAT) Fig. 2 - I2C Timing Diagram Rev. 1.0, 12-Mar-2019 3 Document Number: 84889 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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