Datasheet InnoSwitch3-CE (Power Integrations) - 2

InnoSwitch3-CE DRAIN UNDER/OVER PRIMARY BYPASS (D) INPUT VOLTAGE (V) (BPP) PRIMARY BYPASS REGULATOR ENABLE ENABLE FAULT AUTO-RESTART PRIMARY GATE LINE COUNTER BYPASS PIN INTERFACE RESET BPP/UV UNDERVOLTAGE PRIMARY BPP/UV PRIM-CLK BYPASS PIN + CAPACITOR UV/OV SELECT AND - CURRENT VSHUNT OSCILLATOR/ LIMIT V GATE V TIMERS ILIM JITTER BP+ tON(MAX) tOFF(BLOCK) THERMAL GATE SHUTDOWN GATE PRIM/SEC OV/UV FAULT SecREQ BPP From LATCH-OFF SecPulse SenseFET Secondary PRIM/SEC Power Controller MOSFET Q S DRIVER Q R SEC- RECEIVER LATCH CONTROLLER BPP/UV I t LEB OFF(BLOCK) S ILIM PRIM-CLK + LATCH-OFF PRIMARY OVP VILIM - LATCH tON(MAX)
PI-8044-083017
SOURCE (S)
Figure 3. Primary Controller Block Diagram.
FORWARD SYNCRONOUS RECTIFIER DRIVE OUTPUT VOLTAGE (FWD) (SR) (VOUT) SR CONTROL FORWARD REGULATOR INH 4.4 V ENABLE BPS SECONDARY VOUT SR UV BYPASS (BPS) + - DETECTOR 4.4 V S Q 3.9 V
+
R Q SR THRESHOLD QR HANDSHAKE/ SECONDARY LATCH-OFF CONTROL INH LATCH DCM To FEEDBACK Primary (FB) Receiver FEEDBACK INH + DRIVER - VREF QR CABLE DROP COMPENSATION/ FEEDBACK COMPENSATION TsMAX + - t VPK CONSTANT OFF(MIN) t POWER OSCILLATOR/ SECINH(MAX) TIMER IS THRESHOLD tSS(RAMP) SECONDARY ISENSE GROUND (IS) (GND)
PI-8045a-091217 Figure 4. Secondary Controller Block Diagram.
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Rev. D 08/18 www.power.com Document Outline Product Highlights Description Output Power Table Pin Functional Description InnoSwitch3-CE Functional Description Primary Controller Secondary Controller Applications Example Key Application Considerations Selection of Components Recommendations for Circuit Board Layout Layout Example Quick Design Checklist Absolute Maximum Ratings Thermal Resistance Key Electrical Characteristics Typical Performance Curves InSOP-24D Package Drawing InSOP-24D Package Marking Part Ordering Table MSL Table ESD and Latch-Up Table Part Ordering Information