Datasheet RX65N, RX651 Groups (Renesas)

ПроизводительRenesas
Описание120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 2-MB flash memory
Страниц / Страница246 / 1 — ■ 32-bit RXv2 CPU core. ■ Various communications interfaces. ■ Low-power …
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■ 32-bit RXv2 CPU core. ■ Various communications interfaces. ■ Low-power design and architecture. ■ On-chip code flash memory

Datasheet RX65N, RX651 Groups Renesas

R5F5651EDDBP на РадиоЛоцман.Цены
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ЭлитанRenesasR5F5651EDDBP#20738 руб.

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Features Datasheet RX65N Group, RX651 Group Renesas MCUs R01DS0276EJ0230 Rev.2.30 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 2-MB flash memory Jun 20, 2019 (supportive of the dual bank function), 640-KB SRAM, various communications interfaces including Ethernet MAC, SD host interface (optional), SD slave interface (optional), quad SPI, and CAN, 12-bit A/D converter, RTC, Encryption functions (optional), CMOS camera interface, Graphic-LCD controller, 2D drawing engine Features PLQP0176KB-A 24 × 24 mm, 0.5-mm pitch PLQP0144KA-B 20 × 20 mm, 0.5-mm pitch
■ 32-bit RXv2 CPU core
PLQP0100KB-B 14 × 14 mm, 0.5-mm pitch  Max. operating frequency: 120 MHz PLQP0064KB-C 10 × 10 mm, 0.5-mm pitch Capable of 240 DMIPS in operation at 120 MHz  Single precision 32-bit IEEE-754 floating point  Two types of multiply-and-accumulation unit (between memories PTLG0177KA-A 8 × 8 mm, 0.5-mm pitch PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch and between registers) PTLG0100JA-A 7 × 7 mm, 0.65-mm pitch  32-bit multiplier (fastest instruction execution takes one CPU clock cycle)  Divider (fastest instruction execution takes two CPU clock cycles)  Fast interrupt PLBG0176GA-A 13 × 13mm, 0.8-mm pitch  CISC Harvard architecture with 5-stage pipeline PTBG0064KB-A 4.5 × 4.5mm, 0.5-mm pitch  Variable-length instructions: Ultra-compact code  Supports the memory protection unit (MPU)  JTAG and FINE (one-line) debugging interfaces
■ Various communications interfaces
 Ethernet MAC (1 channel)
■ Low-power design and architecture
 PHY layer (1 channel) for host/function or OTG controller  Operation from a single 2.7- to 3.6-V supply (1 channel) with full-speed USB 2.0 transfer  Low power consumption: A product that supports all peripheral  CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up functions draws only 0.19 mA/MHz (Typ.). to 2 channels)  RTC is capable of operation from a dedicated power supply.  SCIg and SCIh with multiple functionalities (up to 11 channels)  Four low-power modes Choose from among asynchronous mode, clock-synchronous mode,
■ On-chip code flash memory
smart-card interface mode, simplified SPI, simplified I2C, and  Supports versions with up to 2 Mbytes of ROM extended serial mode.  No wait cycles at up to 50 MHz or when the ROM cache is hit, one-  SCIi with 16-byte transmission and reception FIFOs (up to 2 wait state at up to 100 MHz, two-wait state at above 100 MHz channels)  User code is programmable by on-board or off-board programming.  I2C bus interface for transfer at up to 1 Mbps (up to 3 channels)  Programming/erasing as background operations (BGOs)  Four-wire QSPI (1 channel) in addition to RSPIc (3 channels)  A dual-bank structure allows exchanging the start-up bank.  Parallel data capture unit (PDC) for the CMOS camera interface 
■ On-chip data flash memory
Graphic-LCD controller (GLCDC)  2D drawing engine (DRW2D)  32 Kbytes, reprogrammable up to 100,000 times  SD host interface (optional: 1 channel) with a 1- or 4-bit SD bus for  Programming/erasing as background operations (BGOs) use with SD memory or SDIO
■ On-chip SRAM, no wait states
 SD slave interface (optional: 1 channel) with a 1- or 4-bit SD bus for  256K/640 Kbytes of SRAM (no wait states) use with SD host interface  8 Kbytes of standby RAM (backup on deep software standby)  MMCIF with 1-, 4-, or 8-bit transfer bus width
■ Data transfer ■ External address space
 DMACAa: 8 channels  Buses for full-speed data transfer (max. operating frequency of 60  DTCb: 1 channel MHz)  EXDMAC: 2 channels  8 CS areas  DMAC for the Ethernet controller: 1 channel  8-, 16-, or 32-bit bus space is selectable per area  Independent SDRAM area (128 Mbytes)
■ Reset and supply management
 Power-on reset (POR)
■ Up to 25 extended-function timers
 Low voltage detection (LVD) with voltage settings  16-bit TPUa, MTU3a  8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2
■ Clock functions
channels)  External crystal resonator or internal PLL for operation at 8 to 24 MHz
■ 12-bit A/D converter
 Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20  Two 12-bit units (8 channels for unit 0; 21 channels for unit 1) MHz  Self diagnosis, detection of analog input disconnection  120-kHz clock for the IWDTa
■ 12-bit D/A converter: 2 channels ■ Real-time clock

■ Temperature sensor for measuring temperature
Adjustment functions (30 seconds, leap year, and error) 
within the chip
Real-time clock counting and binary counting modes are selectable  Time capture function
■ Encryption functions (optional)
(for capturing times in response to event-signal input)  AES (key lengths: 128, 192, and 256 bits)
■ Independent watchdog timer
 Trusted Secure IP (TSIP)  120-kHz (1/2 LOCO frequency) clock operation
■ Up to 136 pins for general I/O ports ■ Useful functions for IEC60730 compliance
 5-V tolerance, open drain, input pull-up, switchable driving ability  Oscillation-stoppage detection, frequency measurement, CRCA,
■ Operating temp. range
IWDTa, self-diagnostic function for the A/D converter, etc.  D-version: –40C to +85C  Register write protection function can protect values in important  G-version: –40C to +105C registers against overwriting. R01DS0276EJ0230 Rev.2.30 Page 1 of 246 Jun 20, 2019 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 2. CPU 2.1 General-Purpose Registers (R0 to R15) 2.2 Control Registers 2.3 Accumulator 3. Address Space 3.1 Address Space 3.2 External Address Space 4. I/O Registers 4.1 I/O Register Addresses (Address Order) 5. Electrical Characteristics 5.1 Absolute Maximum Ratings 5.2 DC Characteristics 5.3 AC Characteristics 5.3.1 Reset Timing 5.3.2 Clock Timing 5.3.3 Timing of Recovery from Low Power Consumption Modes 5.3.4 Control Signal Timing 5.3.5 Bus Timing 5.3.6 EXDMAC Timing 5.3.7 Timing of On-Chip Peripheral Modules 5.4 USB Characteristics 5.5 A/D Conversion Characteristics 5.6 D/A Conversion Characteristics 5.7 Temperature Sensor Characteristics 5.8 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 5.9 Oscillation Stop Detection Timing 5.10 Battery Backup Function Characteristics 5.11 Flash Memory Characteristics 5.12 Boundary Scan Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice