Datasheet STM32F103x8, STM32F103xB (STMicroelectronics) - 13

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STM32F103x8, STM32F103xB Description 2.2 Full compatibility throughout the family
The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices. Low- and high-density devices are an extension of the STM32F103x8/B devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Low- density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC, while remaining fully compatible with the other members of the STM32F103xx family. The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for STM32F103x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices.
Table 3. STM32F103xx family Low-density devices Medium-density devices High-density devices 16 KB 32 KB 64 KB 128 KB 256 KB 384 KB 512 KB Pinout Flash Flash Flash Flash Flash Flash Flash 6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 KB RAM 64 KB RAM 64 KB RAM
144 - - - - 5 × USARTs 4 × 16-bit timers, 2 × basic timers 100 - - 3 × SPIs, 2 × I2Ss, 2 × I2Cs 3 × USARTs USB, CAN, 2 × PWM timers 3 × 16-bit timers 64 2 × USARTs 3 × ADCs, 2 × DACs, 1 × SDIO 2 × 16-bit timers 2 × SPIs, 2 × I2Cs, USB, FSMC (100 and 144 pins) 1 × SPI, 1 × I2C, USB, CAN, 1 × PWM timer 48 CAN, 1 × PWM timer 2 × ADCs - - - 2 × ADCs 36 - - - DocID13587 Rev 17 13/117 116 Document Outline Table 1. Device summary 1 Introduction 2 Description 2.1 Device overview Table 2. STM32F103xx medium-density device features and peripheral counts Figure 1. STM32F103xx performance line block diagram Figure 2. Clock tree 2.2 Full compatibility throughout the family Table 3. STM32F103xx family 2.3 Overview 2.3.1 ARM® Cortex®-M3 core with embedded Flash and SRAM 2.3.2 Embedded Flash memory 2.3.3 CRC (cyclic redundancy check) calculation unit 2.3.4 Embedded SRAM 2.3.5 Nested vectored interrupt controller (NVIC) 2.3.6 External interrupt/event controller (EXTI) 2.3.7 Clocks and startup 2.3.8 Boot modes 2.3.9 Power supply schemes 2.3.10 Power supply supervisor 2.3.11 Voltage regulator 2.3.12 Low-power modes 2.3.13 DMA 2.3.14 RTC (real-time clock) and backup registers 2.3.15 Timers and watchdogs Table 4. Timer feature comparison 2.3.16 I²C bus 2.3.17 Universal synchronous/asynchronous receiver transmitter (USART) 2.3.18 Serial peripheral interface (SPI) 2.3.19 Controller area network (CAN) 2.3.20 Universal serial bus (USB) 2.3.21 GPIOs (general-purpose inputs/outputs) 2.3.22 ADC (analog-to-digital converter) 2.3.23 Temperature sensor 2.3.24 Serial wire JTAG debug port (SWJ-DP) 3 Pinouts and pin description Figure 3. STM32F103xx performance line LFBGA100 ballout Figure 4. STM32F103xx performance line LQFP100 pinout Figure 5. STM32F103xx performance line UFBGA100 pinout Figure 6. STM32F103xx performance line LQFP64 pinout Figure 7. STM32F103xx performance line TFBGA64 ballout Figure 8. STM32F103xx performance line LQFP48 pinout Figure 9. STM32F103xx performance line UFQFPN48 pinout Figure 10. STM32F103xx performance line VFQFPN36 pinout Table 5. Medium-density STM32F103xx pin definitions 4 Memory mapping Figure 11. Memory map 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Loading capacitor 5.1.5 Pin input voltage Figure 12. Pin loading conditions Figure 13. Pin input voltage 5.1.6 Power supply scheme Figure 14. Power supply scheme 5.1.7 Current consumption measurement Figure 15. Current consumption measurement scheme 5.2 Absolute maximum ratings Table 6. Voltage characteristics Table 7. Current characteristics Table 8. Thermal characteristics 5.3 Operating conditions 5.3.1 General operating conditions Table 9. General operating conditions 5.3.2 Operating conditions at power-up / power-down Table 10. Operating conditions at power-up / power-down 5.3.3 Embedded reset and power control block characteristics Table 11. Embedded reset and power control block characteristics 5.3.4 Embedded reference voltage Table 12. Embedded internal reference voltage 5.3.5 Supply current characteristics Table 13. Maximum current consumption in Run mode, code with data processing running from Flash Table 14. Maximum current consumption in Run mode, code with data processing running from RAM Figure 16. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled Figure 17. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals disabled Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM Table 16. Typical and maximum current consumptions in Stop and Standby modes Figure 18. Typical current consumption on VBAT with RTC on versus temperature at different VBAT values Figure 19. Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V Figure 20. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V Figure 21. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V Table 17. Typical current consumption in Run mode, code with data processing running from Flash Table 18. Typical current consumption in Sleep mode, code running from Flash or RAM Table 19. Peripheral current consumption 5.3.6 External clock source characteristics Table 20. High-speed external user clock characteristics Table 21. Low-speed external user clock characteristics Figure 22. High-speed external clock source AC timing diagram Figure 23. Low-speed external clock source AC timing diagram Table 22. HSE 4-16 MHz oscillator characteristics Figure 24. Typical application with an 8 MHz crystal Table 23. LSE oscillator characteristics (fLSE = 32.768 kHz) Figure 25. Typical application with a 32.768 kHz crystal 5.3.7 Internal clock source characteristics Table 24. HSI oscillator characteristics Table 25. LSI oscillator characteristics Table 26. Low-power mode wakeup timings 5.3.8 PLL characteristics Table 27. PLL characteristics 5.3.9 Memory characteristics Table 28. Flash memory characteristics Table 29. Flash memory endurance and data retention 5.3.10 EMC characteristics Table 30. EMS characteristics Table 31. EMI characteristics 5.3.11 Absolute maximum ratings (electrical sensitivity) Table 32. ESD absolute maximum ratings Table 33. Electrical sensitivities 5.3.12 I/O current injection characteristics Table 34. I/O current injection susceptibility 5.3.13 I/O port characteristics Table 35. I/O static characteristics Figure 26. Standard I/O input characteristics - CMOS port Figure 27. Standard I/O input characteristics - TTL port Figure 28. 5 V tolerant I/O input characteristics - CMOS port Figure 29. 5 V tolerant I/O input characteristics - TTL port Table 36. Output voltage characteristics Table 37. I/O AC characteristics Figure 30. I/O AC characteristics definition 5.3.14 NRST pin characteristics Table 38. NRST pin characteristics Figure 31. Recommended NRST pin protection 5.3.15 TIM timer characteristics Table 39. TIMx characteristics 5.3.16 Communications interfaces Table 40. I2C characteristics Figure 32. I2C bus AC waveforms and measurement circuit Table 41. SCL frequency (fPCLK1= 36 MHz.,VDD_I2C = 3.3 V) Table 42. SPI characteristics Figure 33. SPI timing diagram - slave mode and CPHA = 0 Figure 34. SPI timing diagram - slave mode and CPHA = 1(1) Figure 35. SPI timing diagram - master mode(1) Table 43. USB startup time Table 44. USB DC electrical characteristics Figure 36. USB timings: definition of data signal rise and fall time Table 45. USB: Full-speed electrical characteristics 5.3.17 CAN (controller area network) interface 5.3.18 12-bit ADC characteristics Table 46. ADC characteristics Table 47. RAIN max for fADC = 14 MHz Table 48. ADC accuracy - limited test conditions Table 49. ADC accuracy Figure 37. ADC accuracy characteristics Figure 38. Typical connection diagram using the ADC Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA) Figure 40. Power supply and reference decoupling (VREF+ connected to VDDA) 5.3.19 Temperature sensor characteristics Table 50. TS characteristics 6 Package information 6.1 VFQFPN36 6 x 6 mm, 0.5 mm pitch, package information Figure 41. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package outline Table 51. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data Figure 42. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package recommended footprint Figure 43. VFPFPN36 package top view example 6.2 UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information Figure 44. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline Table 52. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data Figure 45. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint Figure 46. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package top view example 6.3 LFBGA100 10 x 10 mm, low-profile fine pitch ball grid array package information Figure 47. LFBGA100 - 100-ball low-profile fine pitch ball grid array, 10 x10 mm, 0.8 mm pitch, package outline Table 53. LFBGA100 – 100-ball low-profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package mechanical data Figure 48. LFBGA100 – 100-ball low-profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package recommended footprint Table 54. LFBGA100 recommended PCB design rules (0.8 mm pitch BGA) Figure 49. LFBGA100 package top view example 6.4 LQFP100 14 x 14 mm, 100-pin low-profile quad flat package information Figure 50. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline Table 55. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data Figure 51. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package recommended footprint Figure 52. LQFP100 package top view example 6.5 UFBGA100 7x 7 mm, ultra fine pitch ball grid array package information Figure 53. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline Table 56. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data Figure 54. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint Table 57. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) Figure 55. UFBGA100 package top view example 6.6 LQFP64 10 x 10 mm, 64-pin low-profile quad flat package information Figure 56. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline Table 58. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data Figure 57. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint Figure 58. LQFP64 package top view example 6.7 TFBGA64 5 x 5 mm, thin profile fine pitch package information Figure 59. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline Table 59. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid array package mechanical data Figure 60. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid array package recommended footprint Table 60. TFBGA64 recommended PCB design rules (0.5 mm pitch BGA) Figure 61. TFBGA64 package top view example 6.8 LQFP48 7 x 7 mm, 48-pin low-profile quad flat package information Figure 62. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline Table 61. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data Figure 63. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint Figure 64. LQFP48 package top view example 6.9 Thermal characteristics Table 62. Package thermal characteristics 6.9.1 Reference document 6.9.2 Selecting the product temperature range Figure 65. LQFP100 PD max vs. TA 7 Ordering information scheme Table 63. Ordering information scheme 8 Revision history Table 64. Document revision history