Datasheet ADP5070 (Analog Devices) - 7

Data Sheet ADP5070 Pin No. LFCSP TSSOP Mnemonic Description
18 20 SW2 Switching Node for the Inverting Regulator. 19 1 PGND Power Ground for the Boost and Inverting Regulators. 20 2 SW1 Switching Node for the Boost Regulator. EPAD Exposed Pad. Connect the exposed pad to AGND. Rev. D | Page 7 of 27 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PWM MODE PSM MODE UNDERVOLTAGE LOCKOUT (UVLO) OSCILLATOR AND SYNCHRONIZATION INTERNAL REGULATORS PRECISION ENABLING SOFT START SLEW RATE CONTROL CURRENT-LIMIT PROTECTION OVERVOLTAGE PROTECTION THERMAL SHUTDOWN START-UP SEQUENCE APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL COMPONENT SELECTION Feedback Resistors Output Capacitors Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator LOOP COMPENSATION Boost Regulator Inverting Regulator COMMON APPLICATIONS SUPER LOW NOISE WITH OPTIONAL LDOS SEPIC STEP-UP/STEP-DOWN OPERATION LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE