LTC3863 OPERATIONLTC3863 Main Control Loop The resultant differential voltage from VIN to SENSE is The LTC3863 is a nonsynchronous inverting PMOS proportional to the inductor current and is compared to control er, where an inverting amplifier is used to the peak inductor current setpoint. During normal opera- sense the negative output voltage below ground. The tion the P-channel power MOSFET is turned on when the LTC3863 uses a peak current mode control architecture clock leading edge sets the SR latch through the S input. to regulate the output. A feedback resistor, R The P-channel MOSFET is turned off through the SR latch FB1, is placed between V R input when the differential voltage from VIN to SENSE OUT and VFBN and a second resistor, R is greater than the peak inductor current setpoint and the FB2, is placed between VFBN and and VFB. The LTC3863 has a trimmed internal reference, V current comparator, ICMP, trips high. REF, that is equal to (VFB – VFBN). The output voltage is equal to –(RFB1/RFB2) Power CAP and V • V IN Undervoltage Lockout (UVLO) REF where VREF is equal to 800mV in normal regulation. Power for the P-channel MOSFET gate driver is derived The LTC3863 can also be configured as a noninverting from the CAP pin. The CAP pin is regulated to 8V below step-down buck regulator when the VFBN node is pulled V greater than 2V but held less than 5V, which disables the IN in order to provide efficient P-channel operation. The power for the V internal inverting amplifier. A feedback resistor, R CAP supply comes from an internal LDO, FB1, which regulates the V is placed between V IN-CAP differential voltage. A mini- OUT and VFB and a second resistor, mum capacitance of 0.1µF (low ESR ceramic) is required RFB2, is placed between VFB and SGND. In the noninvert- between V ing buck mode the V IN and CAP to assure stability. FB input is compared to the internal reference, VREF, by a transconductance error amplifier For VIN ≤ 8V, the LDO will be in dropout and the CAP volt- (EA). The internal reference can be either a fixed 0.8V age will be at ground, i.e., the VIN-CAP differential voltage reference, VREF, or the voltage input on the SS pin. In will equal VIN. If VIN-CAP is less than 3.25V (typical), the normal operation VFB regulates to the internal 0.8V refer- LTC3863 enters a UVLO state where the GATE is prevented ence voltage. The output voltage in normal regulation is from switching and most internal circuitry is shut down. equal to (RFB1 + RFB2)/RFB2 • 800mV. In order to exit UVLO, the VIN-CAP voltage would have to exceed 3.5V (typical). In soft-start or tracking mode when the SS pin voltage is less than the internal 0.8V reference voltage, VFB will Shutdown and Soft-Start regulate to the SS pin voltage. The error amplifier output connects to the ITH (current [I] threshold [TH]) pin. The When the RUN pin is below 0.7V, the controller and most voltage level on the ITH pin is then summed with a slope internal circuits are disabled. In this micropower shutdown compensation ramp to create the peak inductor current state, the LTC3863 draws only 7µA. Releasing the RUN set point. pin allows a small internal pull-up current to pull the RUN pin above 1.26V and enable the controller. The RUN pin The peak inductor current is measured through a sense can be pulled up to an external supply of up to 60V or it resistor, RSENSE, placed across the VIN and SENSE pins. can be driven directly by logic levels. Rev. B 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
