Datasheet ADL5310 (Analog Devices) - 5

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Data Sheet ADL5310 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS M M F Z G 1 E D M M E T R R O O N U V V C C V O 4 3 2 1 0 2 2 2 2 9 2 1 VSUM 1 18 SCL1 INP1 2 17 BIN1 ADL5310 IRF1 3 16 LOG1 DUAL LOG AMP IRF2 4 15 LOG2 TOP VIEW INP2 5 (Not to Scale) 14 BIN2 VSUM 6 13 SCL2 7 8 9 01 11 21 F S S G G 2 E O O E E T R P P N N U V V V V V O
2
NOTES
00
1. EXPOSED PAD. THE EXPOSED PAD MUST
-0-
BE CONNECTED TO ANALOG GROUND
415
VIA A LOW IMPEDANCE PATH.
04 Figure 2. 24-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Function
1, 6 VSUM Guard Pin. Used to shield the INP1 and INP2 input current lines, and for optional adjustment of the input summing node potentials. Pin 1 and Pin 6 are internally shorted. 2 INP1 Channel 1 Numerator Input. Accepts (sinks) photodiode current IPD1. Usually connected to photodiode anode such that photocurrent flows into INP1. 3 IRF1 Channel 1 Denominator Input. Accepts (sinks) reference current, IRF1. 4 IRF2 Channel 2 Denominator Input. Accepts (sinks) reference current, IRF2. 5 INP2 Channel 2 Numerator Input. Accepts (sinks) photodiode current IPD2. Usually connected to photodiode anode such that photocurrent flows into INP2. 7, 24 VREF Reference Output Voltage of 2.5 V. Pin 7 and Pin 24 are internally shorted. 8, 9 VPOS Positive Supply, (VP – VN) ≤ 12 V. Both pins must be connected externally. 10, 11, 20 VNEG Optional Negative Supply, VN. These pins are usually grounded. For more details, see the General Structure and Applications Information sections. All VNEG pins must be connected externally. 12 OUT2 Buffer Output for Channel 2. 13 SCL2 Buffer Amplifier Inverting Input for Channel 2. 14 BIN2 Buffer Amplifier Noninverting Input for Channel 2. 15 LOG2 Output of the Logarithmic Front End for Channel 2. 16 LOG1 Output of the Logarithmic Front End for Channel 1. 17 BIN1 Buffer Amplifier Noninverting Input for Channel 1. 18 SCL1 Buffer Amplifier Inverting Input for Channel 1. 19 OUT1 Buffer Output for Channel 1. 21, 22 COMM Analog Ground. Pin 21 and Pin 22 are internally shorted. 23 VRDZ Intercept Shift Reference Input. The top of a resistive divider network that offsets VLOG to position the intercept. Normally connected to VREF; may also be connected to ground when bipolar outputs are to be provided. EPAD Exposed Pad. The exposed pad must be connected to analog ground via a low impedance path. Rev. B | Page 5 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS GENERAL STRUCTURE THEORY MANAGING INTERCEPT AND SLOPE RESPONSE TIME AND NOISE CONSIDERATIONS APPLICATIONS INFORMATION CALIBRATION MINIMIZING CROSSTALK RELATIVE AND ABSOLUTE POWER MEASUREMENTS CHARACTERIZATION METHODS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE